Cadence's Synthesizable DDR DRAM PHY is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR DRAM memories. Each configurable PHY is delivered to match the unique requirements of the customer's DDR application. Using Denali's PHY reduces risk and time-to-market for deploying memory interfaces in silicon.
Achieve a GHz PHY including synthesis, layout, and timing closure in 4 hours using a standard EDA toolset
Process node independent
Configurable for data width, ECC, low power, and many other options
"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "