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Synthesizable DDR3/DDR SDRAM PHY in Common Platform 65LPE

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Cadence
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IP Name
DDR3/2/1DDR-SDRAM PHY Common Platform 65LPE
Provider

Cadence
Description

Synthesizable DDR3/DDR SDRAM PHY in Common Platform 65LPE
Categories
Portability
ASIC
Process Node
65nm/Common Platform/LPE    
Type
Soft IP
Maturity
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Overview
Cadence's Synthesizable DDR DRAM PHY is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR DRAM memories. Each configurable PHY is delivered to match the unique requirements of the customer's DDR application. Using Denali's PHY reduces risk and time-to-market for deploying memory interfaces in silicon.
Features
  • Achieve a GHz PHY including synthesis, layout, and timing closure in 4 hours using a standard EDA toolset
  • Process node independent
  • Configurable for data width, ECC, low power, and many other options
  • Supports DDR4, DDR3, DDR2, DDR1, LPDDR2, LPDDR1 devices
  • Silicon-Proven up to DDR-1600 in 28nm
  • Extreme low area
  • Extreme low power
Deliverables
  • Clear, readable, synthesizable RTL
  • Verification test-bench and example tests
  • Synthesis and STA Scripts
  • Comprehensive User Guide
  • Register generation tool
Market Category
Communications, Consumer Electronics, Data Processing, Others
Datasheet
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Protocols
DDR2
DDR3
DDR4
LPDDR2
Gate Count
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QIP Rating
This IP is QIP rated.            This IP is QIP Rated
Customer Testimonial

"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "

James Cheng, Senior Vice President
Global Unichip
 
 
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