Typical security architectures used in SoCs require complete separation of key management and application functions. The Security Protocol
Accelerator—Hardware Security Module (SPAcc-HSM) allows two different security domains, the application and key management processors, to share a single accelerator. Specialized access control modules enforce the security boundary between the application and secure side of the system.
DRM and content protection standards, such as DTCP, demand robust security schemes to protect sensitive key information from non-authorized
use. The SPAcc-HSM provides the required highly-secure infrastructure for key storage and high-throughput cryptographic operations, and at the same time it can be shared securely and reliably with an application processor that has lower security needs.
Features
Single engine shared between application and key management domains
Secure Key module allows the application system to use keys derived in the secure system without visibility to the key data itself
Separate clock domains for the two control interfaces and the cryptographic core
Support for all ciphers, hashes and MAC algorithms used in major protocols such as IPSec, WiMAX, Wi-Fi, 3GPP LTE/LTEA, SRTP, SSL/TLS/DTLS, MACsec, storage
Built-in scatter/gather DMA capability offloads system CPU
Increased throughput through parallel hashing and encryption
Command and status FIFO depth selection offers interrupt coalescence
IV import feature – permits DMA of IV with associated payload
Deliverables
Verilog HDL
Testbench
Sample synthesis script & contstraints
Sample simulation script
Documentation
Market Category
Automotive, Communications, Consumer Electronics, Industrial and Medical, Military/Civil Aerospace