ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog
Visit IP Talks at DAC 2013 to learn the latest about semiconductor IP

Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com

USB 3.0 Host, Device, HUB

Estimate your chip with this semiconductor IP
Synopsys
Semiconductor IP Vendor InformationView all semiconductor IP from SynopsysContact Semiconductor IP VendorSemiconductor IP Customer Testimonials Add Semiconductor IP to an IP List

Share
Email Semiconductor IP Datasheet Print Semiconductor IP Datasheet   
IP Name
VIP, USB 3.0, Host, Device, HUB
Provider

Synopsys

Description

USB 3.0 Host, Device, HUB

Type
Verification IP
Protocols
USB3.0
Design Category
Bus: On Chip
Maturity Status
Available on Request
Overview
Synopsys Verification IP for USB 3.0 is a multi-layered VIP for the verification of USB Hosts, Devices and Hubs with support for SuperSpeed, High Speed, Full Speed and Low Speed Interfaces
Features
  • USB 3.0 and 2.0 including fallback and fall forward
  • Host, Device and Hub Emulation
  • LMP, LPM and ITP generation
  • Cable attach and Detach
  • Supports OTG
  • SS Pipe3. SS Serial and USB 2.0 Serial interfaces
  • Includes Extensive Coverage
  • VMM, UVM and Verilog
Market Category
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
Please login or register to view this data
QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

 
 
     Related IP from Synopsys you may be interested in...
IP Name Description
VIP, USB 1.1, OTG Host USB 1.1, 2.0 and On-the-Go Host
VIP, USB 1.1, OTG Device USB 1.1, 2.0 and On-the-Go Device
VIP, Serial ATA Gen I, SATA 6Gbps Monitor Serial ATA Gen I (1.5 Gbps) Gen II (3.0 Gbps) and SATA 6Gbps Monitor
VIP, Serial ATA Gen I, SATA 6Gbps Device Serial ATA Gen I (1.5 Gbps) Gen II (3.0 Gbps) and SATA 6Gbps Device
VIP, PCI, X-Slave PCI / PCI-X Slave
 
 
Search For Semiconductor Design and Verification IP
Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
SilTerra
SMIC
TSMC
Tower
UMC
X-FAB
advertisement
Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

     Language: Search for Semiconductor Design and Verification IP at ChipEstimate.com English | Search for Semiconductor Design and Verification IP at ChipEstimate.jp Japanese | Search for Semiconductor Design and Verification IP at ChipEstimate.cn Chinese
 
      ChipEstimate.com Chip Planning & IP Portal -- Copyright © 2013 ChipEstimate.com. All rights reserved.
ChipEstimate.com Twitter feed  ChipEstimate.com Semiconductor IP on LinkedIn  ChipEstimate.com Semiconductor IP Channel on YouTube  ChipEstimate.com Semiconductor IP on Facebook  ChipEstimate.com Semiconductor IP on Google+ 


       Feedback  Privacy Policy  Terms of Use  Newsletter & Tech Talk Archive  IP Catalog Site Map