The Digital Blocks DB9000AXI4 TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 4.0 AXI4 Protocol Interconnect to a TFT LCD panel. The DB9000AXI4 contains a selectable 256 / 128 / 64 / 32-bit AXI4 Master Interface and uses the AXI4 higher burst lengths & Quality of Service (QoS) capabilities to target higher resolution, higher color depth TFT LCD panels, with their resulting high frame buffer memory data bandwidth & bounded latency requirements.
The DB9000AXI4 IP Core can be implemented in an ASIC, ASSP, or FPGA device with an embedded microprocessor, an AMBA AXI4 Interconnect fabric, and SDRAM Controller for access to frame buffer memory. Typically, the microprocessor is an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is off-chip DDR / DDR2 / DDR3 SDRAM.
High-Resolution TFT LCD Panel support features by AXI4 Protocol: Up to 16 overlap outstanding reads requests to the SDRAM Controller; Quality of Service (QoS) Support; Programmable burst lengths up to 256 beats; Wide AXI4 Master Port data width, up to 256
Wide range of programmable LCD Panel resolutions: Maximum programmable resolutions of 4096x4096
Example LCD Panel high resolutions: Digital Cinema Systems (DCI) 2048 x 1080 2K image, 4096 x 2160 4K image, & Cinema Scope HD 2560 x 1080, 4096x2560, 3840x2160, 2560x2048, 2048x2048, 2048x1536, 1920x1200, 1920x1080, 1680x1050, 1600x1200, 1600x900
Example LCD Panel medium / small resolutions: 640x480, 640x400, 640x240, 640x200, 480x800, 480x640, 480x272, 480x234, 240x400, 240x320, 240x240, 320x200, 320x240
Interface for 1 Port TFT LCD Panel: 18-bit digital (6-bits/color) , 24-bit digital (8 bits/color) LVDS / CMOS
Interface for 2 Port LVDS TFT LCD Panel: Two 24-bit digital (8 bits/color) LVDS / CMOS ports
Programmable frame buffer bits-per-pixel (bpp) color depths: 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel; 16, 18, bpp directly drive 18-bit LCD pixel; 24 bpp directly drive 24-bit LCD pixel
Color Palette RAM to reduce Frame Buffer memory storage requirements and AXI Bus bandwidth
Programmable Output format support: RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface; RGB 8:8:8 on 24-bit digital interface