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ONFI 3.0 NAND Flash Controller IP

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Arasan Chip Systems
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IP Name
ONFI 3.0 NAND Flash Controller IP
Provider

Arasan Chip Systems
Description

ONFI 3.0 NAND Flash Controller IP
Categories
Portability
ASIC, FPGA
Process Node
all
Type
Soft IP
Maturity
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Overview
NAND Flash is being incorporated into many types of products requiring storage large capacity including portable memory drives, media players, digital cameras, PDAs, digital TVs, digital camcorders and PCs. The Arasan ONFI 3.0 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both SLC and MLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable memory device up to 128 Gb from leading memory providers such as Micron, Samsung, Toshiba, Hynix, ST-Micro, and others. The IP core includes a host of configuration options from page size to band selects. The controller offers Hamming Code (1bit error correction and 2bit error detection) and BCH (option for 4-, 8-, 12-, up to 64 bit error correction) error code correction (ECC) for optimized performance and reliability. Additional features include the capability to boot from flash. The IP core supports the Open NAND Flash Interface Working Group (ONFI) 3.0 standard and is backwards compatible. It uses differential signaling on the clock and data lines and clocks at any frequency up to 200 MHz. The controller supports a variety of host bus interfaces for easy adoption into any design architecture. An optional NAND Flash file system is available to support advanced features. The file system converts complicated tasks of NAND flash memory interfacing to simple memory accesses. Flash memory read, write, garbage collection, bad block management, and other functions are handled by the file system in the background. The cores are delivered in Verilog RTL that can be implemented in an ASIC or FPGA. They are fully tested with vendor models and hardware tested with FPGA-based HDK products. The core includes RTL code, test scripts and a test environment for complete simulation and verification.
Features
  • Supports SDR, NV-DDR and NV-DDR2
  • Supports SLC and MLC devices
  • Supports memories up to 128Gb
  • Supports differential signaling on clock and data lines
  • Up to 400 MT/s
  • Supports warm up cycles for high-speed operation
  • Supports all mandatory commands and selected optional commands
Deliverables
  • RTL design in Verilog.
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documentation
Market Category
Communications, Consumer Electronics, Data Processing
Datasheet
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Bus Interface
AHB/APB - AMBA 2.0 Compliant
Protocols
AMBA 4.0 AHB
AMBA 4.0 APB
Gate Count
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"We have licensed multiple IP Cores from Arasan and have been impressed with the quality of the IP and the support structure that facilitates the internalization and integration of the IP into our chips. Their professional approach and the expertise and know how that they bring along makes all the difference. We got on the bus with Arasan. "

Mohamed Ben-Romdhane, Vice President of Engineering
Newport Media
 
 
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Keywords
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