A-XGMAC provides a 10-Gbps Ethernet Media Access
Controller (MAC) for incorporation in a customer's own ASIC or FPGA-based design. The A-XGMAC module performs the packet transmission and reception protocol as described in IEEE 802.3ae. This includes having a MAC control sublayer as defined in 802.3x. The optional SONET OC-192 data rate control in Clause 46 is also implemented.
The A-XGMAC IP core consists of two different versions of the 10-Gig MAC.
The smaller asymmetric (32-bit Transmit data and 64-bit Receive data) data path version which has been optimized for ASIC implementations and the larger symmetric (64-bit Transmit and Receive data paths) data path version which can be implemented in FPGA-based devices.
Silicon proven 10-Gigabit Ethernet solution since 2002 in over 6 different processes
Provided as reusable technology independent Verilog source code
Low gate count asymmetric (32-bit Transmit data and 64-bit Receive data) data path option or traditional symmetric (64-bit Transmit and Receive data paths) data path version
Support provided for XGMII, XGXS (XAUI), and XSBI interfaces
User configurable Transmit and Receive FIFOs (optional)
Support for complete, FPGA based, layer 2 subsystem
Synthesizable Verilog RTL source code
Functional test bench
Modular level documentation
Synopsis constraint files for synthesis scripts
Annual Support and Maintenance service available after initial support period expires
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others