Real-time High-Quality Video Processing Technology Recovers the Original Interlaced Video Signal

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Silicon Image

IP Name

Progressive Re-Processing (PReP®)

Provider

Silicon Image

Description

Real-time High-Quality Video Processing Technology Recovers the Original Interlaced Video Signal

Category

IP Catalog : Digital Core IP : DSP : Video

Portability

ASIC

Process Node

all

Type

Soft IP

Maturity

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Overview

Progressive Re-Processing (PReP®) is the industry's first technology designed specifically to improve progressive video signals by removing the artifacts caused by inferior interlaced-to-progressive conversion. Video signals that originate in the interlaced format used by most broadcasters often suffer degradation when the signal is converted to the progressive format required by digital displays. If this process is not done well, it results in artifacts which will be amplified during scaling or other processing such as detail enhancement. The patent-pending PReP technology addresses this problem be reverting the progressive video signal to its original interlaced format so that it can be reconverted to progressive using a higher-quality deinterlacer.

Silicon Image's PReP IP core is targeted for use in SoCs for DTVs, computer displays or A/V receivers (sink devices). These devices receive video signals from sources located in front of the video processing chain, such as a set-top box. If the video signal delivered by these sources is poorly deinterlaced, the subsequent device which includes the PReP IP core is able to reprocess the incoming video signal resulting in improved quality. For this functionality, the IP core is placed before the deinterlacer in the video SoC.

The PReP IP works with 8-, 10-, or 12-bit color depth and processes 480p, 576p, 1080p50, and 1080p60 sources. The PReP process can be easily controlled via software.

Features

Industry's first technology to restore progressive video back to its original interlaced format

Works with 480p, 576p, 1080p50, and 1080p60 sources

Eliminates artifacts caused by poor-quality deinterlacers

Software-programmable to enable or disable PReP

8-, 10-, or 12-bit processing

Bypass mode

Deliverables

RTL source code (System Verilog)

C++ model

Test environment

IP core documentation

Market Category

Consumer Electronics

Datasheet

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Gate Count

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QIP Rating

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