MIPI MPHY Receiver Supporting both HS-G1 and HS-G2 modes

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Cosmic Circuits

IP Name

CCHSG1G2MIPIMPHYRX-T28HPM

Provider

Cosmic Circuits

Description

MIPI MPHY Receiver Supporting both HS-G1 and HS-G2 modes

Category

IP Catalog : Analog & Mixed Signal IP : MIPI PHY

Portability

ASIC

Process Node

28nm/TSMC/HPM

Type

Hard IP

Maturity

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Overview

The CCHSG1G2MIPIMPHYTX-T28HPM
integrates a MIPI® MPHY-compatible highspeed
receiver that supports up to 3GHz data
transfer, and a low-power receiver that
supports data transfer in lower power mode.
The IP supports the specifications described
in v1.0 of the M-PHY spec. The lane
management is integrated, and interfaces
with the controller.

Features

Mixed-signal M-PHY hard-macro Receiver solution

Designed to MIPI® v1.0 MPHY specification

MPHY RMMI interface supports UFS, CSI-3, SSIC, DigRF and LLI protocols

Supports high-speed gears HS-G1A, HSG1B, HS-G2A, HS-G2B

2.9152Gbps maximum data transfer rate per lane

Supports both SYS and PWM mode LS operation

Supports PWM gears PWM-G0 through PWM-G5

Maximum low-speed data rate of 144Mbps per lane in PWM-G5

Supports terminated and non-terminated operation, integrates switchable termination

Built-in support for Optical Media Converters (OMCs)

Deliverables

Verilog models, GDSII, Netlist (Spice format for LVS)

Footprint (LEF format), Behavioral verilog model, User documentation

Module integration guidelines, Datasheet

Silicon validation report (where available)

Evaluation board

Market Category

Communications, Consumer Electronics, Others

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

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