Cadence's Flash DLL PHY supports 4 different DDR Flash Standards: ONFI 2, ONFI 3, Toggle 1, Toggle 2,In addition the PHY supports a bypass mode to support asynchronous Flash memories including ONFI1. Cadence's DLL DDR PHY is an all-digital solution connecting the DDR I/O pads to the DFI interface of the memory controller including alignment of write data, read data capture, and DQS gating. By using an all-digital DLL-based design, both power and area are kept to a minimum, typically under 4mW per data slice for ONFI 3 mode 7 . For consumer, low-power, wireless, handheld and battery-operated devices, Cadence's DDR DLL PHY is a small, power-efficient PHY design supporting all modes of operation as per ONFi specifaction. The soft PHY gives complete flexibility over process, library, floorplan, I/O pitch, packaging, metal stack-up, routing, and other physical parameters, offering the user total control of the DDR interface implementation. The architecture of Cadence's DLL DDR PHY is a classic DQS-delay architecture with a 10-year history of reliable design-ins. It has been created for ease of implementation and to be highly compatible with EDA tools from multiple vendors. An automated design flow allows RTL to placed gates can be achieved in as little as 4 hours using the advanced synthesis and STA scripts included with the design. It uses a DFI ver. 2 with NAND extensions as an interface.
ASIC, FPGA, Structured
Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others
DFI 2.0 with NVM extensions
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