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DDR Reference Regulator

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S3 Group
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IP Name
S3REG115GF18
Provider

S3 Group
Description

DDR Reference Regulator
Categories
Portability
ASIC
Process Node
180nm/GLOBALFOUNDRIES
Type
Hard IP
Maturity
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Overview
The S3REG115GF18 is a reference regulator circuit
which has been designed to provide 0.625-0.99V with
a load current of up to 1mA, having a low area and
high accuracy.
Features
  • 180nm GF Process
  • 1.5V Input Voltage
  • 0.625V – 0.99V Output Voltage
  • 1mA Max Load Current
  • Power good detection
  • Low area
Deliverables
  • Integration Support
  • Datasheet, Characterization Report
  • Flat Netlist (cdl), Abstract View (lef)
  • Layout View (gds2), Timing (lib)
  • Behavioral Model (Verilog)
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
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Size
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"S3 helped us to enter volume production rapidly by achieving first-time-right silicon resulting in a best-in-class performance product. The high level of integration achieved has made it possible to offer customers a low-cost bill of material solution that perfectly meets our customers' requirements. One of the key benefits of engaging with S3 was their ability to combine their silicon-proven IP and professional services to deliver complete solutions. "

Dirk Wieberneit, VP & General Manager of Product Development
Micronas
 
 
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Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
 SilTerra
SMIC
TSMC
 Tower
UMC
X-FAB
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Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

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