Dual channel operation Transceiver for WAVE_EU, WAVE_US, WAVE_JP, DSRC_JP and IEEE 802.11a/p

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Catena

IP Name

WAVE and IEEE 802.11a Transceiver

Provider

Catena

Description

Dual channel operation Transceiver for WAVE_EU, WAVE_US, WAVE_JP, DSRC_JP and IEEE 802.11a/p

Categories

IP Catalog : Analog & Mixed Signal IP : RF : Transceiver

IP Catalog : Analog & Mixed Signal IP : Analog Front Ends

IP Catalog : Digital Core IP : Subsystems : Platform IP

Portability

ASIC, Structured

Process Node

65nm/GLOBALFOUNDRIES/65LPe

Type

Hard IP

Maturity

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Overview

The Catena WAVE transceiver architecture is based on direct conversion for both the transmitter and receiver, which eliminates expensive and external filters. Internal digitally controlled AGC:s provides a low noise, high dynamic range receiver and a transmitter with wide range output power . The baseband filters are calibrated with the internal tuning loop and the filter supports modulation bandwidths between 1.75 – 20 MHz. An internal Crystal Oscillator is implemented to allow the use of a low cost crystal. A clock output buffer is implemented to deliver a reference frequency for the baseband chip or a potential second WAVE transceiver. Two independent data paths are implemented. Each data path includes a fractional N synthesizer and support for two frequency bands. Control of the transceiver is done via a four wire SPI interface or via a five wire JTAG interface. To support fast gain control, RX/TX switching and frequency hopping a high speed parallel interface is supported. An internal auxiliary ADC is implemented for calibration purposes and to serve various external functions like power and temperature measurements.

Features

Dual channel operation with two independent synthesizers.

Two frequency band supported: 715 - 725MHz and 5.18 - 5.93GHz.

Two transmitters and receivers for each frequency band.

2x2 MIMO.

Integrated calibration algorithms.

1.5-2.5 V Analog supply with integrated regulators.

Low current consumption.

Development platform with Catena BB processor in FPGA.

0 dBm linear OFDM transmit power.

Low Noise Figure

Deliverables

Data sheet upon request

Hard Macro

Technology transfer

SoC integration support

Market Category

Automotive, Communications, Consumer Electronics, Industrial and Medical

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

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