AHB VIP in native SystemVerilog (UVM/OVM/VMM)

Estimate your chip with this semiconductor IP

Avery Design Systems

IP Name

AHB-Xactor

Provider

Avery Design Systems

Description

AHB VIP in native SystemVerilog (UVM/OVM/VMM)

Type

Verification IP

Simulator

NC, VCS, Questa

Supported Language

SystemVerilog UVM/OVMVMM

Protocols

AMBA 2.0 AHB
AMBA 4.0 AHB

Design Category

Bus: On Chip

Maturity Status

Released

Overview

AHB-Xactor is a widely proven solution enabling SoC and IP developers to perform comprehensive functional verification of their AHB master, slave, and interconnect designs and ensure compliance to the AHB standard. The solution consists of BFMs, compliance testsuites, protocol checking, functional coverage monitors, and producer-consumer scoreboard. BFM components and testsuites are all provided in SystemVerilog OVM/UVM/VMM in partial or full source code format. The BFMs support complex traffic sequence generation and all-layer error injection to verify normal and error behvaiors. Compliance testsuites support the AHB compliance protocol checkers from ARM. Compliance verification services are also available from Avery.

Features

Comprehensive support for AMBA AHB including BFMS for master, slave, and N-port interconnects

Complex traffic sequence generators for normal and error scenarios

Robust API to program complex and random BFM request/response timing and operational behaviors and error injection

Producer-Consumer scoreboard performs end2end verification and protocol checking

Complete compliance testsuites including directed and constrained random testsuites

Supports all verification methodologies including VMM, OVM, UVM

Works directly with the ARM AMBA AHB Protocol Checker releases for comprehensive assertion-based verification

Packet tracker monitors output and improves debug

Models and test suites licensed in SystemVerilog partial or full source code formats

Proven with multiple IP vendors

Deliverables

BFM components, Producer-Consumer scoreboard

Complaince testsuites in source code format

Compliance checklist test plan

User Guide

Market Category

Automotive, Consumer Electronics

Datasheet

Please login or register to view this data

Bus Interface

AHB

QIP Rating

This IP is not yet QIP rated.

Related IP from Avery Design Systems you may be interested in...

	IP Name			Description
	PCI-Xactor			PCIe VIP in native SystemVerilog (UVM/OVM/VMM) and Verilog
	AXI-Xactor			AXI 3/4 VIP in native SystemVerilog (UVM/OVM/VMM)
	USB-Xactor			USB VIP in native SystemVerilog (UVM/OVM/VMM)
	UAS/BOT-Xactor			UAS/BOT VIP in native SystemVerilog (UVM/OVM/VMM)
	MIPI-Xactor			MIPI VIP in native SystemVerilog (UVM/OVM/VMM)