UAS/BOT VIP in native SystemVerilog (UVM/OVM/VMM)

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Avery Design Systems

IP Name

UAS/BOT-Xactor

Provider

Avery Design Systems

Description

UAS/BOT VIP in native SystemVerilog (UVM/OVM/VMM)

Type

Verification IP

Simulator

NC, VCS, Questa

Supported Language

SystemVerilog UVM/OVMVMM

Protocols

Ultra SCSI
Ultra-320 SCSI
Ultra-640 SCSI
Ultra2 SCSI
Ultra3 SCSI
USB1.1
USB2.0
USB3.0

Design Category

Storage: HDD

Maturity Status

Pre-Release

Overview

UAS/BOT-Xactor is a widely proven solution enabling SoC and IP developers to perform comprehensive functional verification of their UASP/BOT USB device designs and ensure compliance to the USB-IF UAS, BOT, and SCSI SPC/SBC/SAM standards. The solution consists of BFMs, compliance testsuites, protocol checking, functional coverage monitors, and producer-consumer scoreboard. BFM components and testsuites are all provided in SystemVerilog OVM/UVM/VMM in partial or full source code format. The BFMs support complex traffic sequence generation and all-layer error injection to verify normal and error behvaiors. Compliance testsuites support the USB-IF UAS and BOT compliance test specifications, Microsoft SCSI tests, and additional protocol checking provided by Avery. Compliance verification services are also available from Avery.

Features

Comprehensive support for UAS 1.0, BOT MSC, SCSI SPC-4, SBC-3, and SAM-5 including UAS and BOT host driver BFMs that interface to Avery USB host or actual xHCI host controller (via xHCI VIP)

Complex traffic sequence generators for normal and error scenarios

Functional coverage of SCSI command types and throughput

Robust API to program complex and random BFM request/response timing and operational behaviors and error injection

Producer-Consumer scoreboard performs end2end verification and protocol checking

Complete compliance testsuites including directed and constrained random testsuites and extensive protocol Checking based on Avery based checklists

Supports all verification methodologies including VMM, OVM, UVM

Command, UAS/BOT stage, and USB pipe trackers monitor output at all levels to improve debug

Models and test suites licensed in SystemVerilog partial or full source code formats

Proven with multiple IP vendors

Deliverables

BFM components, Producer-Consumer scoreboard

Complaince testsuites in source code format

Compliance checklist test plan

User Guide

Market Category

Consumer Electronics

Datasheet

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Bus Interface

USB

QIP Rating

This IP is not yet QIP rated.

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