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High Density Power Optimization Kit Full, GF 55LP LVt

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Synopsys
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IP Name
Logic Libraries, Power Optimization, High Density, GF 55LP LVt
Provider

Synopsys
Description

High Density Power Optimization Kit Full, GF 55LP LVt
Categories
Portability
ASIC
Process Node
55nm/GLOBALFOUNDRIES/LP
Type
Hard IP
Maturity
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Overview
Synopsys' DesignWare® Logic Libraries portfolio includes the SiWare® Logic and ASAP Logic cell libraries. The SiWare Logic product line includes yield-optimized standard cells for a wide array of design applications from 65 nm to 28 nm process nodes with multiple threshold process variants. The ASAP Logic product line consists of metal programmable and standard cell libraries designed to meet the highest quality and performance standards for 180 nm to 90 nm process nodes.
Deliverables
  • .lib
  • LEF
  • GDS
  • Verilog
  • CDL and other industry standard design views
Market Category
Communications, Consumer Electronics, Data Processing, Military/Civil Aerospace, Others
Datasheet
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Size
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans
 
 
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Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
 SilTerra
SMIC
TSMC
 Tower
UMC
X-FAB
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Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

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