This block connects between four GMII ports and a 5GHz SerDes. The four data streams are multiplexed over a single serial data stream according to the QSGMII spec. The block is intended for MAC side operation and can detect link status information for each port supplied by the PHY.
Supports a 10- or 20-bit SerDes interface
Features as per QSGMII Specification revision 1.2 published by Cisco Systems
10, 100M and 1G operation
Gigabit operation uses GMII and 10/100M operation uses MII
8b/10b encoding/decoding on transmit/receive data for each lane
Uses transmit buffers for reliable sampling of data from the G/MII interface to the internal clock domain
Supports transport of Low Power Idle indication as described in IEEE 802.3az
Synthesizable Verilog RTL
Verilog testbench and scenarios
Cadence synthesis scripts with SDC constraints
User Guide and programming manual
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
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