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Gigabit Ethernet - PCS for Quad-Serial Media Independent Interface (QSGMII PCS)

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Cadence
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IP Name
PCS for Quad-Serial Media Independent Interface (QSGMII PCS)
Provider

Cadence

Description

Gigabit Ethernet - PCS for Quad-Serial Media Independent Interface (QSGMII PCS)

Category
Portability
ASIC, FPGA, Structured
Process Node
all
Type
Soft IP
Maturity
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Overview
This block connects between four GMII ports and a 5GHz SerDes. The four data streams are multiplexed over a single serial data stream according to the QSGMII spec. The block is intended for MAC side operation and can detect link status information for each port supplied by the PHY.
Features
  • Supports a 10- or 20-bit SerDes interface
  • Features as per QSGMII Specification revision 1.2 published by Cisco Systems
  • 10, 100M and 1G operation
  • Gigabit operation uses GMII and 10/100M operation uses MII
  • 8b/10b encoding/decoding on transmit/receive data for each lane
  • Uses transmit buffers for reliable sampling of data from the G/MII interface to the internal clock domain
  • Supports transport of Low Power Idle indication as described in IEEE 802.3az
Deliverables
  • Synthesizable Verilog RTL
  • Verilog testbench and scenarios
  • Cadence synthesis scripts with SDC constraints
  • User Guide and programming manual
Market Category
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
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Bus Interface
GMII
Protocols
Ethernet
Gate Count
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "

James Cheng, Senior Vice President
Global Unichip

 
 
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