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DisplayPort v1.2 Transmitter IP Core

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HDL Design House
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IP Name
DisplayPort v1.2 Transmitter IP Core
Provider

HDL Design House

Description

DisplayPort v1.2 Transmitter IP Core

Categories
Portability
ASIC, FPGA
Process Node
all
Type
Soft IP
Maturity
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Overview
This IP is VESA DP1.1a, DP1.2 and eDP compliant with four
main lanes and an auxiliary channel. The DP transmitter
works at DP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data
rates, but it can also support the turbo (3.24Gbps) and
HBRII (5.4Gbps) modes of the DP1.2 standard.
The IP is composed of the DP 1.2 TX controller core and its
physical layer device (PHY), in 65nm, 40nmLP, and
28nmLP technologies.
Features
  • DP SST and MST compliant
  • Supports video format in RGB, YCbCr 4:4:4/4:2:2, xvYCC, Adobe RGB
  • Deep color up to 16 bits per component, HSync, VSync, Field ID and DE
  • Supports dual bus video
  • Audio ports: up to 4 I2S, SPDIF
  • Audio sampling rates: Up to 192 KHz
  • Supports HDCP data encryption
  • Supports DP 1.2 side band and GTC messages, as well as 3D and SDP nesting
Market Category
Communications, Consumer Electronics, Data Processing
Datasheet
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Gate Count
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"We are delighted to work with HDL DH in the development of our HDMI digital video solution. Because of their extensive expertise, quality of work, and total commitment to the customer, HDL DH has been selected as Transwitch preferred design and verification contractor, and we look forward to working with them in our future projects. "

Amir Bar-Niv, Vice President of Systems and Applications
TranSwitch Corporation

 
 
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Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
SilTerra
SMIC
TSMC
Tower
UMC
X-FAB
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Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

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