XpressRICH3 - Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC

PLDA

XpressRICH3 - Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC

• IP Catalog : On-Chip Bus IP : PCI Express

• Complies with the PCI Express® Base 3.0 Draft Specification, rev.3.0
• Supports Endpoint, Root-Port, Dual-Role, Switch configurations
• Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
• Implements one Virtual Channel with a maximum payload size of up to 4KB
• Built-in clock domain management
• User Interface: Tx/Rx for data, 256-bit data path, user-selectable frequency, Sideband interfaces for configuration, debug, monitoring, advanced features and TL bypass interface for switch/bridge implementations
• PHY Interface: PIPE 3.0 compliant , 32bit/250MHz in Gen3 mode and 16-bit mode supported
• Multi-Function, AER, ECR, ATS/PRI and MSI, MSI-X
• ASPM and legacy power management
• Lane Reversal, Hot Plug and Atomic operations

• XpressRICH3 IP with Synthesizable Verilog RTL source code, Simulation libraries for functional simulation and Configuration assistant GUI
• PCI Express Bus Functional Model including Simulation libraries
• Software Design Kit with PCI Express Linux device driver (binary or source code), C API and Reference design text executable and C++/Java source code
• Reference design with Synthesizable Verilog RTL source code, Simulation environments and test scripts and Synthesis environment and scripts
• Complete technical documentation and technical support and maintenance