Truechip's AMBA AXI4 Verification IP provides an effective & efficient way to verify the components interfacing with AMBA AXI4 bus in an ASIC/FPGA or SOC.
Availability of Test Suites enables the designers to focus on features unique to their design.
Features
Compliant to AMBA® AXI 4 specifications from ARM
Parameterized data and address bus
Configurable wait states on different channels
Support all variants of AXI4
Internal Architechture Based on TLM 2.0
Supports wide variety of error injection scenarios
AXI4 Verification IP comes with Extensive Coverage Across the Channels
Supports FIFO, memory and Cache Model integrated
Supports out of order transaction with Parameterized out of order width
Supports data interleaving on read data channel
Deliverables
AMBA AXI4 Master/Slave Agent
AMBA AXI4 Bus Monitor and ScoreBoarding
AMBA AXI4 Interconnect Model (Optional)
AXI4–AXI3/AHB (& vice versa) Gasket Model (Optional)
Test Suites: Basic, Directed & Random, Assertions and Coverage Point Tests