Truechip's MIPI CSI-2 Verification IP provides an
effective & efficient way to verify the components
interfacing with MIPI CSI-2 interface of an ASIC/FPGA or SoC.
Truechip's MIPI CSI-2 VIP is fully compliant with
Stardard MIPI CSI-2 rev. 1.01 specifications from MIPI Alliance.
Features
Compliant to MIPI CSI 2 Interface Specification, Revision 1.01
Configurable from 1 to 4 Data Lanes
Programmable Multi-lane Merging
Support all primary and secondary CSI-2 Data formats
Supports PPI interface to D-PHY
32-Bit Pixel Output format
User can configure MIPI CSI-2 number of lanes, line coding, Continous Clock behavior and Low Power Escape as well as ULPS mode using CCI Commands
Supports Dynamic as well as Static Error Injection scenarios
Supports option to configure CSI-2 using CCI commands
Strong Protocol Monitor with Real time exhaustive programmable checks available for each LLP, LM and PHY layer