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MIPI PLL

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Mixel
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IP Name
MXL-PLL-MIPI-PXL
Provider

Mixel
Description

MIPI PLL
Category
Portability
ASIC
Process Node
40nm/TSMC
Type
Hard IP
Maturity
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Overview
The MXL-PLL-MIPI-PXL is a high performance PLL based frequency synthesizer implemented using digital CMOS technology. It is highly integrated and requires no external components. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip.
The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design. The MXL-PLL-MIPI-PXL incorporates a Lock Detector, three programmable output dividers, and supports a full-power down mode.
Features
  • All output programmable dividers produce 50% duty cycle for both even and odd divisors
  • High performance, highly programmable MIPI Pixel PLL
  • Low power dissipation
  • High frequency, low jitter output
  • Three programmable output frequencies
  • Glitch-free transition outputs
Deliverables
  • Data Sheet/Specfications
  • GDS2
  • LEF
  • Timing Model
  • Verilog Model
Market Category
Communications, Consumer Electronics
Datasheet
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Size
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Mixel and Northwest Logic's leadership position in the MIPI IP's PHY and Controller markets respectively, was one of the factors that influenced our decision. The firstsilicon success and the outstanding support that we have received during multiple tape-outs validated this important choice. We're looking forward to a long-term collaboration with both companies. "

Yusuke Yamamoto, Senior Manager, Mkt & Strategic Planning Dept
Kawasaki Microelectronics
 
 
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Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
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Foundry
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Portability
ASIC FPGA Structured
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