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PCIe PHY, CP 65G, x4 - FC

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Synopsys
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IP Name
PCI Express (PCIe) PHY, CP 65nm G
Provider

Synopsys
Description

PCIe PHY, CP 65G, x4 - FC
Categories
Portability
ASIC
Process Node
65nm/Common Platform/G    
Type
Hard IP
Maturity
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Overview
The DesignWare PHY IP for PCI Express 2.0, operating at 5.0 Gbps, meets the demand for increased bandwidth and narrower interconnect links in the data center, storage and networking infrastructure applications. Compatible with the PCIe 2.0 and PIPE specifications, it allows designers to optimize performance and power while maintaining interoperability with existing devices. The IP exceeds electrical specification in areas such as jitter, margin and receive sensitivity, delivering a robust design without sacrificing performance. Also included are advanced built-in diagnostic capabilities and ATE test vectors which require no special process options, provides ease of integration and high production yields. As the leading provider of PCI Express IP, Synopsys offers the IP industry's only complete, silicon-proven PCI Express 2.0 IP solution, including digital controllers, PHY and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 5.0 Gbps PCI Express interface into their high performance SoC designs.
Features
  • Doubles the data transfer speed from 2.5 Gbps to 5.0 Gbps
  • Compliant with the PCI Express 2.0 (5.0 Gbps) and 1.1 (2.5 Gbps) specifications
  • Backwards compatible with PCI Express 1.1
  • Designed for integration in root complex, endpoint, dual-mode and switch applications
  • Exceeds electrical specifications in areas of margin and receive sensitivity for a robust design
  • Unique, built-in diagnostics enables visibility into link performance
  • Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing
  • Industry's only complete PCI Express 2.0 IP solution: digital controllers, PHY and verification IP
  • Supports advanced 65-nm processes with roadmap to 40nm processes
Deliverables
  • GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
  • Simulation model for digital blocks, Behavioral models for analog blocks
  • Synopsys' PrimeTime STA results, Gate-level netlist and SDF timing file
  • DesignWare PHY Hard Macro Databook for PCIe
  • BSDL files for JTAG AC/DC Boundary Scan, ATE test vectors
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
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Size
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans
 
 
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Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
 SilTerra
SMIC
TSMC
 Tower
UMC
X-FAB
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Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

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