Cadence NVMe PCie Sub System

Estimate your chip with this semiconductor IP

Cadence

IP Name

Cadence NVMe Sub System

Provider

Cadence

Description

Cadence NVMe PCie Sub System

Categories

IP Catalog : On-Chip Bus IP : SATA

IP Catalog : Digital Core IP : Controllers : Cache

IP Catalog : Off-Chip Interface IP : Bus Interface IP : PCI Express

Portability

ASIC, FPGA, Structured

Process Node

all

Type

Soft IP

Maturity

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Overview

Cadences NVMe sub system is 1.0 rev C compliant and the first in the industry to offer a hardware end to end solution from PHY to SoC fabric. To complete the sub system a software stack that enables setup and initialization and command processing is also included to form a complete sub system solution. This offers many advantages to the SoC design team by offering a complete verified sub system block that terminates at a known point for HW as well as a defined API interface for system software. The bus interconnects between PHY, PCIe controller and NVMe are already optimized and require no additional logic.

Features

The number of I/O Queues supported can be configured up to the maximum of 65536 Queues.

Support PCIe features such Bifurcation, SRVIO, MIMO and others

Support for Weighted Round Robin with Urgent Arbitration Mechanism

PCIe is Fully configurable FIFOs and RAMs along with several configuration options such as ECC, end-to-end datapath parity, ECRC support

Admin Queue commands to create or delete I/O Queues are handled autonomously without local firmware support

Support for up to 256 functions (physical (PF) or virtual (VF)) with ARI support

Support for X1 up to X16 lane configurations with X16 configuration performing dual-packet processing per cycle for maximum throughput

Software abstracts all NVMe controller functionality for a local CPU with minimal application assistance, and performs sub system initialization and all commands that are not hardware accelerated.

Deliverables

Readable and commented RTL, fully regressed by Cadence for each delivery

Synthesis Scripts and STA script

Basic Test Bench

Firmware stack in C source code

Software, Hardware User Guides and Documents

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace

Datasheet

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Bus Interface

Open

Protocols

AMBA 3.0 AXI
AMBA 4.0 AXI
ONFI 3.0
PCIe
SAS
SATA3.0
SCSI
SRIO

Gate Count

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QIP Rating

This IP is QIP rated.

Customer Testimonial

"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "

James Cheng, Senior Vice President
Global Unichip

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