Ultra-low jitter, dual voltage ring PLL

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Silicon Creations

IP Name

Programmable Low Jitter PLL - UMC 55nm

Provider

Silicon Creations

Description

Ultra-low jitter, dual voltage ring PLL

Categories

IP Catalog : Analog & Mixed Signal IP : Clock : PLL

IP Catalog : Analog & Mixed Signal IP : Clock : Clock Synthesizer

Portability

ASIC, Structured

Process Node

55nm/UMC/SP

Type

Hard IP

Maturity

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Overview

Multi-function, general purpose frequency synthesizer. Wide input and output ranges along with best-in-class jitter performance makes this PLL suitable for clocking high-end ADC and AFE circuits. By combining ultra-low jitter output clocks into a low power, low area, widely programmable design.

Features

Input Frequency Range: 10MHz to 640MHz

Output Frequency Range: 14MHz to 2.8GHz

4:1 VCO frequency range allows PLL to be optimized for minimum jitter or minimum power

Differential (CML) output enables low-jitter output clock path

Integrated Long Term Jitter as low as 1ps RMS

Reference spur better than -65dBc

Phase Noise better than –120dBc/Hz (100kHz offset, 156.25MHz carrier)

Ultra-fast locking time of 1000 reference cycles

Isolated analog supply allows for excellent supply rejection in noisy SoC applications

Low Area (0.07mm2)

Deliverables

GDSII

Calibre LVS Netlist

Behavioral Verilog Model with true loop dynamics and jitter

LEF Footprint, LIBERTY Timing Models

Detailed Application Note

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

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