OTP/eMTP: 64 Kbit NVM in 65nm Standard Logic CMOS process

Estimate your chip with this semiconductor IP

Sidense

IP Name

SiPROM_TSMC65LP25_2Kx32_1S4Y2_AF

Provider

Sidense

Description

OTP/eMTP: 64 Kbit NVM in 65nm Standard Logic CMOS process

Categories

IP Catalog : Digital Core IP : Memories : Non-volatile RAM

IP Catalog : Digital Core IP : Memories : EEPROM

IP Catalog : Digital Core IP : Memories : eFuse

Portability

ASIC, Structured

Process Node

65nm/TSMC/LP

Type

Hard IP

Maturity

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Overview

OTP (One-Time Programmable) or eMTP (Emulated Multiple-Time Programmable) memory IP available in a standard logic CMOS process requiring no additional masks or process steps. Replacement for eFuse, Flash and mask ROM. Non-volatile memory (NVM) IP is available in a wide range of configurations (8 Kbits to several Mbits) for a broad range of analog and digital applications including encryption and security keys, IDs, code storage, digital rights management (including HDMI) and analog trimming.

Features

No Additional Masks or Process Steps

Very Secure & Reliable

Low voltage operation

Access times down to 10ns

Secure Program Lock Function

>20 years retention

Programmable on Tester, at Wafer probe, or in the Field

Low power

Very Small Area

Wide I/O width 8 to 128 bitsGDS Database

Deliverables

GDS Database

Verilog Models

.lib files

Full Data Sheet

Application Notes

Market Category

Automotive, Communications, Consumer Electronics, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

Serial/Parallel

Size

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"We chose Sidense OTP for code storage in our Telran transceiver platform due to its small footprint, low power consumption and scalability to advanced process nodes for future designs. Sidense OTP helps us to deliver devices to our customers that maximize battery life and meet their performance needs. "

Alison Burdett, CTO
Toumaz Microsystems

View More Testimonials

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	NVM-512Kbit-65nm-GP-TSMC			OTP/eMTP 512 Kbit NVM in 65nm Standard Logic CMOS process
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