VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM, Memory Array Range:128 to 2Mega Bits

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VeriSilicon

IP Name

GSMC18_LPDROM_01

Provider

VeriSilicon

Description

VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM, Memory Array Range:128 to 2Mega Bits

Category

IP Catalog : Digital Core IP : Memories : ROM

Portability

ASIC

Process Node

180nm/Grace

Type

Hard IP

Maturity

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Overview

VeriSilicon GSMC 0.18um Synchronous Low Power Diffusion ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/Analog 1P6M Industry Baseline Generic (IBG) 1.8/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands. The compiler supports a comprehensive range of word length and bit length. While satisfying Low Power and speed requirements, it has been optimized for area efficiency. VeriSilicon GSMC 0.18?m Synchronous Low Power Diffusion ROM compiler uses four metal layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are synthesized in with the intention to enhance reliability.

Features

Low Power

High Density

Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time

Automatic Power Down

More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Others

Datasheet

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Size

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QIP Rating

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