The DDRC-3010 is a high performance memory controller that provides a highly configurable interface to external Double Data Rate Synchronous DRAM (DDR3 DRAM). It can support up to 8 AXI User ports with an intelligent scheduler that is optimized for very high throughput. It also includes a CPU port that is optimized for low latency and timing critical transactions. DDRC-3010 can support data rates up to 2133 Mbps.
The DDR3 memory controller can support a wide variety of memory devices and organizations including standard DDR3 DIMMs like UDIMM, RDIMM, etc. The memory controller supports all the memory functions including automated initialization, self-refresh, auto-refresh and power-down etc. The various DDR3 timing parameters are programmable. It can be configured to optionally support ECC, command /address parity and 1T/2T timing.
The DDR3 memory controller has a highly intelligent scheduler that includes multiple algorithms to improve the memory throughput. The scheduler improves the memory throughput by reordering requests and minimizing the effects of various DDR internal operations like precharge/refresh, etc. The controller can support BL8 (burst length) or BC4 (burst chop) on-the-fly to improve memory throughput.
The memory controller supports DDR PHY Interface (DFI v2.1) to ease the integration of DDR PHY. It supports the DFI frequency ratios of 1:2 and 1:4.
Up to 2133 Mbps operation
Compliant to JEDEC DDR3 (JESD79-3E)standards
Support for standard DDR3 DIMMs - RDIMM
Support for x4, x8 and x16 memories
Support for up to 8 ranks (CS#)
Support for 1T and 2T timing
On-the-fly support for BL8 and BC4
Low latency (3 cycles or less)
Highly-configurable DDR parameters
Programmable DDR timing parameters
Synthesizable RTL code
Synthesis and STA scripts
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace