Hybrid Memory Cube (HMC) represents an entirely new category of high-performance memory, delivering revolutionary performance and power in a dramatically reduced footprint.

Open Silicon's HMC Controller IP provides the industry's first, highest performance and most flexible solution for integrating the many benefits of HMC technology into next-generation systems.

Open-Silicon's HMC Controller IP is a high-performance, flexible soft macro implementation of the Micron HMC Generation 2 Interface Protocol. The design provides system designers with the fastest, lowest risk solution for interfacing to the Hybrid Memory Cube.

The Open-Silicon HMC IP supports the Micron HMC Generation 2 Interface. As one of the developer members of the HMC Consortium, Open-Silicon plays a key role in developing the HMC Interface Specification and roadmap, as well as enabling industry application and ecosystem development.

Designed and tested to be easily synthesizable into 45nm - 22nm ASIC technologies, Open-Silicon's HMC IP Core was uniquely built to seamlessly interface with SerDes from leading technology vendors. This allows Open-Silicon customers to quickly integrate the HMC IP Core into their process technology and SerDes vendor of choice.