High-speed 14-bit ADC

Estimate your chip with this semiconductor IP

NTLab

IP Name

1090IP1_ADC_HS_01P1

Provider

NTLab

Description

High-speed 14-bit ADC

Categories

IP Catalog : Analog & Mixed Signal IP : A2D Converter

IP Catalog : Analog & Mixed Signal IP : Other

Portability

ASIC

Process Node

90nm/TSMC/CMOS

Type

Hard IP

Maturity

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Overview

This ADC has architecture of pipelined ADC, pipeline ADC consists of a cascade of stages, each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (multiplying digital-to-analog converter, MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. This ADC consist of bias, lvds clock receiver, ADC core, output logic correction block. The ADC requires 1.6 Ã· 2 V analog supply and 0.9 Ã· 1.1 V digital supply, there are standby mode which allow to optimize power consumption for system need. Also exist tuning of ADC operating mode by digital correction registers: register ref<3:0> specify differential reference range (refp and refn) , register iadc<2:0> specify tuning of ADC currents, register ish<2:0> specify tuning of sample-and-hold currents, exist possibility to use external voltage source for differential reference refp and refn.

Features

TSMC 90nm CMOS LP technology

Resolution 14 bit

Conversion rate 50 MSPS

Using different power supply 1 V for digital and 1.8 V for analog parts of ADC circuitry

Standby mode (current consumption <5 uA)

Power dissipation from 62 mW to 314.2 mW

Spurious-free dynamic range 87 dB

Deliverables

Schematic, Layout

Extracted view

GDS

Test bench with saved configurations

Documentation

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Others

Datasheet

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Size

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QIP Rating

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