IBM 32nm USB 2.0 PHY

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VeriSilicon

IP Name

I32SOIV18_USB20PHY_01

Provider

VeriSilicon

Description

IBM 32nm USB 2.0 PHY

Category

IP Catalog : Analog & Mixed Signal IP : USB PHY

Portability

ASIC

Process Node

32nm/Common Platform

Type

Hard IP

Maturity

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Overview

The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB analog front-end with a build-in 8-bit/16-bit parallel interface, therefore, it is easy to interface with USB2.0 Device System. It can work either as a host PHY or as a device PHY, depending on the different setting from controller.

Features

Process: IBM 32nm SOI process

Supply voltage: 0.9v+/-10%, 1.8v +/-10%, 3v~3.3v

Operating junction temperature: - 40Â°C ~ +25Â°C ~ +125Â°C

Compliant with the USB Spec Rev2.0

Compliant with the UTMI Spec Rev1.05

Compliant with the UTMI+ Level 3 (None OTG features and None HUB features)

Supports 480Mbit/s "High Speed" and 12Mbit/s "Full Speed"

Supports 60MHz/8-bit interface and 30MHz/16-bit interface

12MHz/24MHz external crystal, internal oscillator and PLL are used for generating

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Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

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