Cadence provides mature and comprehensive verification IP (VIP) for USB protocols. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM). Incorporating the latest protocol updates, our USB VIP provides a complete bus functional model with integrated automatic protocol checks, a coverage model for collecting simulation results, and an extensive library of compliance tests. Designed for easy integration in testbenches at IP, SoC, and system levels, Cadence® VIP for USB protocols helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality. USB 3.0 Verification Cadence VIP for USB protocols has been used extensively in the verification of SuperSpeed (USB 3.0) designs. VIP features include: • Full timing bus functional modeling of the USB 3.0 specification • Verifies host, device, and hub designs • Supports OTG 3.0 operation • Operates in SuperSpeed mode • Supports backward-compatibility with USB 2.0 in high- and full-speed modes • Provides full stack verification as well as PIPE-MAC and PIPE-PHY verification • Provides full power management support • Simplifies protocol compliance verification via automated stimulus generation and coverage reporting • Monitors, checks, and collects coverage on bus traffic using automatic protocol checks, including configuration and runtime checks • Provides a complete USB protocol hierarchy enumeration process • Provides access to and control of callbacks, packets, and memory mapped registers • Supports bulk, control, interrupt, and isochronous transfers and bulk streaming protocol • Supports all engineering change notices (ECNs) to specification • Enables error injection at each layer • Handles system-level errors including error detection, reporting, and logging SuperSpeed InterChip (SSIC) Cadence VIP for USB protocols supports the SSIC interface, which uses MIPI M-PHY specification as the physical layer. Cadence was a leader in developing VIP for SSIC and worked closely with USB-IF and MIPI Alliance standards groups on early versions of the specification. VIP features include: • Support for x1, x2, and x4 lane configu- rations • Supports serial physical interface • HS-G1, HS-G2, and HS-G3 bursts with data rate series A/B • LS mode support with PWM-G1 burst • Provides access to M-TX and M-RX capabilities and attributes through memory-mapped registers • Supports all M-PHY states as per SSIC specification (SLEEP, STALL, HIBERN8, HS-BURST, PWM-BURST, etc.) USB 2.0 Verification Cadence VIP for USB protocols has been used extensively in the verification of USB 2.0 designs as well. VIP features include: • Full timing, bus functional modeling of the USB 2.0 specification • Verifies host, device, and hub designs • Supports OTG operation • Backwards-compatible with USB 1.1 specifications • Operates at high, full, or low speed • Completely models the protocol, and manages transaction requests and responses • Checks for all transaction and packet rules • Models the physical link from the protocol layer to the simulation environment • Supports DP/ DM, UTMI, UTMI+, ULPI, and HSIC interfaces • Supports reset, suspend/resume, remote wakeup, and LPM • Supports SRP and HNP compliance checking for USB OTG • Supports bulk, control, interrupt, and isochronous transfers, as well as split transactions PureSuite PureSuite provides an extensive library of SystemVerilog-UVM tests that are easy to implement. The quick bring-up reduces time to first test and the large test suite accelerates compliance testing. Each PureSuite test includes a detailed description of purpose, assumptions, scenarios, and expected results. Tests are driven from the VIP across the protocol interface toward the design under test or can be initiated from the application interface of the design. Capabilities include: • Supports USB 2.0 and USB 3.0 host, device, and PHY verification • Tests all protocol layers and key state machines • Includes verification plan for measuring verification progress • Built-in functional coverage • Extensive set of pre-built tests for exercising the design under test • Error recovery testing • Tests configurable based on implemen- tation of design under test • Supports all major simulators Accelerated VIP In addition to supporting logic simulation, optional Accelerated VIP is available to enable simulation acceleration with the Palladium XP hardware accelerator. Simulation acceleration combines the verification capabilities of logic simulation with the speed of acceleration to deliver performance up to 100x the speed of logic simulation. This performance improvement enables extensive verifi- cation of SoCs that would be too large for meaningful logic simulation.
Full timing, bus functional modeling of USB specification
Models host, device and hub
Full Support to all layers (framework, protocol, link, and physical)
Support dual-simplex, four-wire differential signaling and 8b/10b parallel interface
Operates in SuperSpeed, Full, or HighSpeed mode
Detailed coverage of functional layers
Complete USB enumeration
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "