AMBA Assertion Based VIP (ABVIP) with Compliance Solution

Estimate your chip with this semiconductor IP

Cadence

IP Name

VIP, AMBA, AHB Assertion Based

Provider

Cadence

Description

AMBA Assertion Based VIP (ABVIP) with Compliance Solution

Type

Verification IP

Simulator

3rd Party

Supported Language

e, SV

Protocols

AMBA 2.0 AHB
AMBA 4.0 AHB

Design Category

Bus: On Chip

Maturity Status

Pre-Release

Overview

The Cadence AMBA Family of Verification IP (VIP) provides a mature, highly capable compliance verification solution for ARM®'s full set of AMBA® protocols including AMBA 3 and AMBA 4 Stream and AXI4. Having verified over 2,000 production designs, you can depend on the AMBA VIP's maturity. It supports a range of verification platforms making it applicable to IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence Incisive Enterprise Simulator as well as the Synopsys VCS® and Mentor Graphics Questa® simulators. The AMBA VIP supports the unique Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results correlated directly to the protocol specification. IP developers. Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. SoC developers. One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification. System developers. Use accelerated VIP to take advantage of the speed of Palladium hardware systems to verify hardware/software integration. In addition, the Virtual Register Interface enables software to drive the testbench. Supported Configurations The VIP provides agents to verify all AMBA components including masters, slaves, arbiters and decoders. The VIP supports all configurations including multiple masters, multiple slaves and combinations of masters and slaves. All AHB configurations such as Lite and Multi-Layer. Protocol Compliance The AMBA VIP provides a highly capable protocol compliance verification solution called the Compliance Management System. CMS includes a verification plan and a full suite of tests. It drives defined, constrained random bus traffic at all layers to offload this time consuming task from you. Injected errors and error conditions are flagged and recovered according to AMBA specifications. The VIPs sequence generation engine applies a context-sensitive approach to test plan execution. This greatly speeds the verification task and increases verification productivity. A cumulative coverage database ensures that the design under test is sufficiently exercised. Verification Platform Choice Cadence VIP provides users the greatest range of platforms to use for AMBA verification. In addition to the simulation VIP described above, Cadence also provides assertion based verification IP (ABVIP) and accelerated VIP for the Palladium Verification Computing Platform. Details on each are provided below. Formal Verification Cadence's AMBA Assertion Based Verification IP (ABVIP) is available for AXI and AHB. ABVIP takes advantage of the speed and efficiency of the Incisive Formal Verifier platform (IFV) to provide an easy to use, highly predictable path to verification closure. Through powerful formal analysis techniques the AMBA ABVIP enables design engineers to easily verify AXI and AHB functionality and compliance since there is no need for them to create test stimulus. ABVIP contains complete and optimized constraint and assertion models and a set of pre-verified PSL properties and cover checks. They are used for interface monitoring in simulation and exhaustive formal analysis of protocol compliance with IFV. Hardware Acceleration Cadence supports accelerated verification using the Palladium XP Verification Computing Platform. This provides users with the performance needed for system level verification. It also enables users to trade off performance for verification capability as they progress from block to chip to system level verification. Cadence Accelerated VIP supports two different use modes: DirectC and UVM acceleration. The DirectC acceleration mode provides the absolute highest performance without a testbench. The UVM acceleration mode provides simulation environment reuse and a higher degree of verification capability relative to DirectC. This enables users to trade off performance and verification capability to meet their needs at each stage in the design process. Language & Methodology Support The following languages may be used in conjunction with the VIP: • SystemVerilog • e • SystemC • Verilog • VHDL • C,C++ The following methodologies may be used in conjunction with the VIP: • UVM • OVM • VMM • eRM Customer Feedback "We brought up the CMS compliance test suite in our verification environment in just a day. Our team was impressed with the rapid results. We identified a number of failures right away and we are now working to dramatically expand our regression runs to take full advantage of the CMS." Mike Bartley Test and Verification Manager, ClearSpeed ARM Feedback The strength of AMBA has always been centered around its broad industry adoption and EDA support. As a leading EDA company, Cadence has enabled the embedded community with AMBA-based design and verification tools for years, and we look forward to their continued strong support for our newest AMBA 4 on-chip interconnect specification.ÃƒÆ'Ã¢â‚¬Å¡Ãƒâ€šÃ‚Â Keith Clarke Vice President and General, Fabric IP Processor Division at ARM Take a Self-Guided Tour Test drive this VIP on-line via the hands-on demos at Xuropa.com

Features

Supports AMBA 4 and AMBA 3 including Stream, AXI3/4, AHB and APB

Compliance Management System automates protocol compliance verification

Generates constrained-random bus traffic

Responds to bus traffic as a slave

Monitors, checks, and collects coverage on bus traffic and interconnect

Includes hundreds of assertions for formal compliance verification

Supports SystemVerilog, e and SystemC language test benches

Operates in both simulated and accelerated platforms for ultimate flexibility

Complies with the Unified Verification Methodology (UVM)

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

AMBA AHB

QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "

James Cheng, Senior Vice President
Global Unichip

View More Testimonials

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