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Single-Port, Low Voltage, TSMC 65LP, HVt & SVt, SRAM Memory Compiler

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Mobile Semiconductor
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IP Name
Single Port, Low Voltage TSMC 65LP SRAM Compiler
Provider

Mobile Semiconductor
Description

Single-Port, Low Voltage, TSMC 65LP, HVt & SVt, SRAM Memory Compiler
Categories
Portability
ASIC
Process Node
65nm/TSMC/LP
Type
Hard IP
Maturity
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Overview
Mobile Semiconductor's Trailblaze(TM) software delivers silicon-proven SRAM compilers to generate low voltage (LV), ultra high speed (UHS), multi-megabit (MM) and high density (HD) memory architectures.

Mobile Semiconductor's low-voltage (LV) design techniques enable a wider range of operating voltages and a wider range of standby voltages for minimal power consumption. Mobile Semiconductor low-voltage memory compilers use back biasing to reduce array leakage and ensure read and write operations with minimal power supply voltages. SRAMs are generated with the industry's leading experience in bit cell stability and statistical analysis for yield and leakage. High threshold voltage devices are used to minimize leakage currents, and limited standard threshold voltage devices are used when required. Low-voltage SRAMs operate at minimal power and have ultra-low power standby capabilities to extend useful battery lives of end products.

Mobile Semiconductor's ultra-high speed (UHS) design techniques deliver the highest operating speeds while keeping die sizes small. Proprietary silicon-proven design and layout techniques are applied to achieve high performance architectures in low power processes. Low threshold voltage and standard threshold voltage devices are used to optimize the critical path, enhancing performance while limiting static current. Mobile Semiconductor's industry-leading design techniques increase soft error immunity and utilize statistical timing analysis for optimal yield.

Mobile Semiconductor's multi-megabit (MM) macro compilers generate multi-megabit SRAM macro-block instantiations using high density SRAM instances. The memory macro compiler can generate L-shaped or rectangular footprints for flexibility in SOC floorplanning, while eliminating the need for iterative synthesis, place-and-route experimentation and aspect ratio analysis.

Mobile Semiconductor's commercial SRAM compilers use standard high density 6T bit cells and are consistent with Design for Manufacturing (DFM) process guidelines. Column redundancy is offered to further enhance yield. Trailblaze(TM) programmable Built-in Self Test (BIST) Compilers are available for seamless integration of verification. Industry standard BIST views are also available. Mobile Semiconductor's highest level of industry expertise offers both off-the-shelf and custom low-voltage, high-performance, optimized SRAM memory compilers.
Features
  • Power Mesh Architecture
  • Internal BIST Mux
  • Functional, BIST & Scan Operational Modes
  • Selectable Aspect Ratio
  • Bit Write Enable
  • Selectable Column Redundancy
  • Configurable Read/Write Timing Margins
Deliverables
  • Compilers generated by the Trailblaze(TM) software create the necessary views to seamlessly integrate into industry-standard design flows.
  • PDF & Text Datasheets
Market Category
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
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Size
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QIP Rating  This IP is not yet QIP rated.
 
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