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PCIE Gen3 PHY - TSMC 28 HPM

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Cadence
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IP Name
PCIe Gen3 PHY - TSMC 28 HPM
Provider

Cadence
Description

PCIE Gen3 PHY - TSMC 28 HPM
Categories
Portability
ASIC
Process Node
28nm/TSMC
Type
Hard IP
Maturity
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Overview
This SerDes PHY macro is designed in TSMC 28nm technology to specifically meet the PCIE GEN3 standard. This hard macro can be paired with Cadence PCIe Controller to provide a complete PCIE solution. Test features include CMOS scan chains, JTAG boundary scan, line and serial loop back, BIST, analog test bus, and AMBA digital interface for programming. The macro will operate from 0ºC to 125ºC and is designed for a flip-chip package.
Features
  • Supports Gen1, Gen2 and Gen3 applications
  • Supports x1x2,x4,x8 and x16 configurations
  • Automatic calibration of analog circuits and offset correction for improved BER
  • Fully adaptive CTLE
  • JTAG, Scan and AMBA test interface
  • Multi-tap DFE and FIR filter
  • BIST functions for manufacturing tests
  • Multiple loop back options
  • IBIS-AMI model
  • On-chip eye diagram and eye margin capability
Deliverables
  • Detailed specification
  • LIB timing view, LEF, GDSII
  • Integration support
  • Behavioral model and test benches
  • Verification file LEC, DRC, LVS and ANT
Market Category
Consumer Electronics
Datasheet
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Bus Interface
JTAG and AMBA
Size
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "

James Cheng, Senior Vice President
Global Unichip
 
 
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Node
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