This SerDes PHY macro is designed in TSMC 28nm technology to specifically meet the PCIE GEN3 standard. This hard macro can be paired with Cadence PCIe Controller to provide a complete PCIE solution. Test features include CMOS scan chains, JTAG boundary scan, line and serial loop back, BIST, analog test bus, and AMBA digital interface for programming. The macro will operate from 0Ãƒâ€šÃ‚ÂºC to 125Ãƒâ€šÃ‚ÂºC and is designed for a flip-chip package.
Supports Gen1, Gen2 and Gen3 applications
Supports x1x2,x4,x8 and x16 configurations
Automatic calibration of analog circuits and offset correction for improved BER
"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "