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Low jitter (<1ps RMS), low power Integer-N Digital PLL in 55/65nm CMOS

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Cambridge Analog Technologies
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IP Name
CAT-PLI-CBC-55
Provider

Cambridge Analog Technologies
Description

Low jitter (<1ps RMS), low power Integer-N Digital PLL in 55/65nm CMOS
Categories
Portability
ASIC
Process Node
40nm
Type
Hard IP
Maturity
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Overview
The CAT-PLI-CBC-55 is a digital phase-locked loop with ultra-low jitter. It is ideally suited for applications that require low power consumption with ultra-low jitter performance in a compact area, such as in ADC clocking, low-power SERDES, and other power-constrained wireline applications.
Features
  • Low power operation
  • Tiny silicon footprint
  • Integrated testing capability
  • Fast settling time
  • Good jitter performance
  • Option of divided outputs or reference frequencies
  • Also available in 65nm CMOS
Deliverables
  • Fully characterized hard GDS (gds2)
  • Spectre netlist and behavioral models (to enable SoC simulations)
  • Abstract view at layout level (for top level connectivity)
  • Datasheets
  • Integration application notes and support
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
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Size
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QIP Rating  This IP is not yet QIP rated.
 
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IP Name Description
CAT-PLI-CBC-40 Low jitter (<1ps RMS), low power Integer-N Digital PLL in 40nm CMOS
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Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
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ASIC FPGA Structured
IP Quality
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