The broadband flash analog-to-digital converter IP includes two 9-bit broadband analog-to-digital converters in parallel, in which the two ADC's share a reference ladder, a bias block, a clock generator and digital I/Os. The flash ADC architecture is based on a patented time-domain interpolation scheme that reduces loading of the track-and-hold amplifier (THA), enabling high-speed operation without sacrificing resolution, while simultaneously achieving smaller area and lower power consumption.
The track-and-hold circuit at the front-end makes the clock distribution manageable by having the clock jitter requirement relaxed and makes it easier to track the signal before the quantization. It takes a fully differential signal and keeps the differential signal path for reducing the effect of power supply ripple, ground bounce, and common mode signals.
To mitigate the comparator offsets and delay variation of the time-domain interpolators, the ADC IP uses a background comparator offset calibration and a patented delta-sigma based delay calibration to achieve the 9-bit resolution.
A patented time-domain interpolation technique for small area and low power consumption
Background offset and delay calibrations for the 9-bit SNR performance
Testbus for probing internal signals
Three parallel output data streams at 1/3 clock speed
Silicon-proven in the TSMC 45/65 nm CMOS processes
1.21 V power supply
Analog input signal bandwidth: 800 MHz
Power consumption 250 mW per ADC
0.9 V p-p differential analog input
48 dB SNR
Data sheet upon request
SoC integration support
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace