MIPI MPHY Transmitter supporting up to 3Gbps (HS-G2) data-rate meant for DigRFv4, UFS, CSI-3 applications

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Cosmic Circuits

IP Name

CCHSG1G2MIPIMPHYTX-T65LP

Provider

Cosmic Circuits

Description

MIPI MPHY Transmitter supporting up to 3Gbps (HS-G2) data-rate meant for DigRFv4, UFS, CSI-3 applications

Categories

IP Catalog : Analog & Mixed Signal IP : MIPI PHY

IP Catalog : Digital Core IP : Controllers : MIPI

IP Catalog : On-Chip Bus IP : MIPI

Portability

ASIC

Process Node

65nm/TSMC/LP

Type

Hard IP

Maturity

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Overview

The CCHSG1G2MIPIMPHYTX-T65LP
integrates a MIPI M-PHY transmitter that
supports data-rates up to 3000Mbps per
lane and a low-speed transmitter that
supports both SYS and PWM modes. The
IP is based on Version 1.4 of the MIPI MPHY
specifications. The RMMI interface is
integrated and interfaces with CSI-3,
DigRFv4, LLI, SSIC and UFS controllers.
The implementation is modular and up to 4
lanes can be connected in parallel to
increase the through-put.

Features

MIPI M-PHY TX solution

M-PHY based on v1.4

M-PHY RMMI interface supports CSI-3, DigRFv4, LLI, SSIC and UFS Protocols

High-Speed 3000Mbps data transfer per lane

Modular implementation with lane scalability up to 4 lanes

Supports both SYS and PWM mode LS operation

Slew-rate control for EMI reduction

Supports terminated and non-terminated operation

Low power dissipation

Compact foot print, TSMC 65 LP process

Deliverables

GDSII, Netlist (Spice format for LVS)

Footprint (LEF format), User documentation

Module integration guidelines, Datasheet

Silicon validation report (where available)

Evaluation board (where available)

Market Category

Communications, Consumer Electronics, Data Processing, Others

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

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