Parallel NOR Flash Controller IP Core

Estimate your chip with this semiconductor IP

CAST

IP Name

PFLASH-CTRL

Provider

CAST

Description

Parallel NOR Flash Controller IP Core

Category

IP Catalog : Digital Core IP : Memories : Flash

Portability

ASIC

Process Node

all

Type

Soft IP

Maturity

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Overview

This memory controller core is a configurable module designed to interface an AMBA AHB bus to an external, parallel NOR Flash memory device. It bridges a 32-bit AHB system bus to a generic external bus that can be connected to almost any parallel NOR Flash device.

Designed for ease of use, the memory controller core allows word, half-word, and byte width addressing to 32-bit, 16-bit, and 8-bit Flash devices. Also, the number of read and write wait-states and the memory size are configurable to allow proper communication with different Flash devices. Software drivers and modified interfaces are available on request. The PFLASH-CTRL core is production proven and available in RTL source or as a targeted FPGA netlist.

Features

Enables easy integration and control of random access NOR Flash memory in processor-based systems.

Bridges parallel NOR-Flash interface to AMBA 2.0 bus.

AHB Slave Data Interface: Byte, 16 bit half-word and 32 bit accesses Designed to provide maximum throughput

APB Slave Control/Status Interface

Wide support of parallel NOR-Flash devices Programmable access times 8, 16, or 32 bit data bus

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Gate Count

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"iSine provides custom ASIC and SoC solutions to multiple market segments (see www.isine.com). The quality and support of CAST IP cores have saved us valuable time to market with these products. In this highly competitive environment, this advantage is critical to the success of our company. CAST has repeatedly and quickly helped us out of last-minute jams and multi-vendor IP interface issues. "

Robert Gross, Senior Engineer
iSine, Inc.

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