Synopsys' DesignWare USB 2.0 PHY IP solution provides designers with the industry's best combination of low area and low power with support for the leading 45-, 65-, 90-, 130- and 180-nm process technologies. The DesignWare USB 2.0 PHY solution consists of the USB 2.0 picoPHY, USB 2.0 nanoPHY, USB 2.0 HSIC-LPM PHY and the USB 2.0 OTG PHY. The DesignWare USB 2.0 IP is the most certified IP solution in the industry. With over 2,000 design wins and hundreds of millions of silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.
Ported to over 50 different processes and configurations ranging from 180-nm to 28-nm
USB nanoPHY and USB picoPHY offers a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
USB 2.0 PHYs support Device, Host and OTG configurations
GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
Simulation model for digital blocks, Behavioral models for analog blocks
Synopsys' PrimeTime STA results, Gate-level netlist and SDF timing file
DesignWare USB 2.0 PHY Databook
Digital test vectors (.wgl); scan test environment with Automatic Test Pattern Generation (ATPG) vectors
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "