ONFI3.0 Universal Flash Controller (PE - UFC 3.0) IP provides an interface to NAND, NOR, SRAM and Serial flash devices. The UFC has an AXI/AHB/APB (configurable – default AHB) slave interface to
connect to the SoC. The data from the external devices (Flash or Serial peripheral) can be transferred from using register I/O – Programmed IO Mode (PIO) or using DMA mode. The UFC can work up to 80 MHz of serial interface and up to 400 MHz on the NAND interface. To ensure less overhead for the Host processor controlling the data transfers, multiple commands can be queued.
The Controller can queue up to 32 commands and will have 1024 byte deep data buffers for data transfer. The UFC is designed to meet timing very easily at all the interfaces.
Compliant to ONFI3.0, AMBA -AHB, APB 2.0, AXI 2.0
Supports SDR modes[0-5], NV-DDR modes[0-5] and NV-DDR2 modes[0-7]
Interleaved Page Program / Read and Erase Operations Multiple LUN / Plane operations