ONFI 3.0 Universal Flash Controller

Estimate your chip with this semiconductor IP

Posedge Inc.

IP Name

PE - UFC 3.0

Provider

Posedge Inc.

Description

ONFI 3.0 Universal Flash Controller

Categories

IP Catalog : On-Chip Bus IP : ONFI 3.0

IP Catalog : Digital Core IP : Controllers : Bus

IP Catalog : Digital Core IP : Memories : Flash

Portability

ASIC, FPGA

Process Node

all

Type

Soft IP

Maturity

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Overview

ONFI3.0 Universal Flash Controller (PE - UFC 3.0) IP provides an interface to NAND, NOR, SRAM and Serial flash devices. The UFC has an AXI/AHB/APB (configurable – default AHB) slave interface to
connect to the SoC. The data from the external devices (Flash or Serial peripheral) can be transferred from using register I/O – Programmed IO Mode (PIO) or using DMA mode. The UFC can work up to 80 MHz of serial interface and up to 400 MHz on the NAND interface. To ensure less overhead for the Host processor controlling the data transfers, multiple commands can be queued.

The Controller can queue up to 32 commands and will have 1024 byte deep data buffers for data transfer. The UFC is designed to meet timing very easily at all the interfaces.

Features

Compliant to ONFI3.0, AMBA -AHB, APB 2.0, AXI 2.0

Supports SDR modes[0-5], NV-DDR modes[0-5] and NV-DDR2 modes[0-7]

Interleaved Page Program / Read and Erase Operations Multiple LUN / Plane operations

Programmable page size – 512B, 2KB, 4KB, 8KB, 16KB

Supports ECC Enable and Disable options

Supports BCH Code (up to 40bit error correction)

Supports programmable setup, access, hold, and transition times for NOR flash

Supports toggle Mode

SPI master interface at 80 MHz

Supports Boot/XIP mode,mode0, mode3 and Programmable CPOL, CPHA

Deliverables

Fully synthesizable RTL/Unencrypted Source Code

Self checking Test-bench and Test cases

Verification specification

Simulation Scripts –NCVerilog, VCS, Modelsim Questasim

ASIC/FPGA synthesis scripts , User Documentation

Market Category

Automotive, Communications, Consumer Electronics

Datasheet

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Bus Interface

APB/AHB/AXI/ONFI

Protocols

AMBA 2.0 AHB
AMBA 2.0 APB
AMBA 3.0 AXI
ONFI 3.0
SPI-3
SPI-4.1
SPI-4.2

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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