Ultra HD / 3D Full HD Display Processor

Estimate your chip with this semiconductor IP

Evatronix

IP Name

PANTA DP20

Provider

Evatronix

Description

Ultra HD / 3D Full HD Display Processor

Categories

IP Catalog : Digital Core IP : Audio/Video : Format Conversion

IP Catalog : Digital Core IP : Controllers : LCD

IP Catalog : Digital Core IP : DSP : Video

Portability

ASIC, FPGA, Structured

Process Node

all

Type

Soft IP

Maturity

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Overview

The PANTA DP20 display processor is the backend module of a digital video path intended for use in real-time multi-display systems. The design has been optimized for high-end mobile devices by implementation of power reduction methods.
The PANTA DP20 provides support for 3 independent input layers with programmable size, offset and format. Also the output timing and resolution are fully programmable and give possibility for up to 8K display formats (e.g. Ultra HD or DCI 4K).
The PANTA DP20 supports various YUV and RGB color spaces, also with several subsampling modes (4:4:4, 4:2:2, 4:2:0). Moreover, it implements advanced composition modes using layer and pixel alpha-blending methods.
The PANTA DP20 is equipped with the AMBA® AXI4 master interface to provide effi cient, low-latency communication with the system memory.
Flexible and easy programming of the display processor is provided by two AMBA® APB interfaces – one for general purpose and the other for secure
access.

Features

Programmable custom display resolution up to 8191x8191 pixels

On-the-fl y composition of up to 3 video and graphics layers

Interoperability with the ARM® TrustZone® environment

Plethora of supported RGB and YUV pixel formats

Support for 3D HDMI formats

HDMI and MIPI DPI compatible interface

AMBA® AXI4 read master interface

Programmable number of outstanding transactions (up to 32) and burst length (up to 256)

One pass operation to minimize the system memory bandwidth

Power Save Mode via AXI Lowpower interface or by software

Deliverables

Verilog source code

Synthesis support (Synopsys®, Cadence®) with a complete set of synthesis scripts

Simulation support (Mentor Graphics®, Cadence®) with a full set of scripts and macros

Extensive SystemC testbench

Documentation

Market Category

Consumer Electronics

Datasheet

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Bus Interface

AXI

Protocols

AMBA 4.0 APB
AMBA 4.0 AXI
HDMI

Gate Count

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Fujitsu Telecommunications Europe was recently presented with a major product re-design issue that required a significant number of its design and development processes to be fast-tracked against a very aggressive timeframe. We engaged with Evatronix to assist us in this endeavour and were highly impressed with the responsiveness, quality of work and professionalism of the company. We would quite happily work with Evatronix in the future. "

Mark Hanvey, Director of Procurement
Fujitsu Telecommunications Europe Ltd

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