The multi-channel, multi-protocol DesignWare® Enterprise 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth. Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nm Enterprise 10G PHY supports multiple interface standards, including 10GBASE-KR and PCI Express® (PCIe®) 3.0, for a flexible interconnect solution. The DesignWare IP also implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet, giving designers a proven, scalable solution to address the growing demand for additional networking bandwidth in high-speed systems-on-chips (SoCs). Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the standards' electrical specifications. The PHY is small in area and provides a low-power, cost-effective solution to meet the needs of applications with high-speed chip-to-chip, board-to-board, and backplane interfaces. The Enterprise 10G PHY reduces both product development cycles and the need for costly field support by employing internal test features. The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into actual channel performance. The PHY integrates seamlessly with the DesignWare digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.
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