The Digital Blocks DB8051C-SP (Standard Peripherals) Microcontroller Verilog IP Core is complaint with the MCS®51 Instruction Set and contains standard 8051 MCU peripherals, including an interrupt controller, UART, two 16-bit timers, and four 8-bit I/O ports. The DB8051C-SP builds on the highly successful DB8051C CPU Core, utilizing Digital Blocks Instruction Overlap Architecture, which results in a small VLSI footprint and low Clocks Per Instruction high performance.
Digital Blocks companion 8051 IP, the DB8051C-CP (Configurable Peripherals), customizes the peripherals to the unique requirements of the user application (any combination of interrupts, UARTs, timers, I/O ports) and adds I2C, SPI, CAN communications capabilities.
Streamlined for ASIC, ASSP & FPGA Integration, the RTL microarchitectural choices include Registered RAMs, Hardware Micro Control Unit, Unidirectional Busses, & a Fully Static, Rising Edge Only, Synchronous Design.
8-bit Microcontroller Binary Compliant with MCS 51 Instruction Set
Standard 8051 Architecture: Arithmetic / Logical Unit, Hardware Multiply / Divide, Boolean Processor for Bit Manipulation, 5 Addressing Modes
Enhanced 8051 Architecture: minimum 3 Cycles Per Instruction Execution
Up to 256 bytes of internal Data Memory
Program Memory: User Defined, up to 64 KB (more with Memory Banking); NVM or Configurable SRAM
Data Memory: User Defined, up to 64 KB
Standard Peripherals: interrupt controller, UART Serial Port, two 16-bit timers, and four 8-bit I/O ports
Power Management Unit
Streamlined ASIC & ASSP & FPGA Integration: Registered RAMs, Hardwired (No RAM) Micro Control Unit
Fully synthesizable, static synchronous design, single edge clocking, and no internal tri-states. Scan test ready
Verilog RTL Source
Comprehensive testbench suite with expected results
Technical Reference Manual
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace