The Digital Blocks DB8051C-CP (Configurable Peripherals) Microcontroller Verilog IP Core is complaint with the MCS®51 Instruction Set and contains configurable peripherals, including an interrupt controller with up to 64+6 interrupt sources, timers, UART, I2C, SPI, CAN, PWM unit, Keyboard Controller, and I/O ports. The DB8051C-CP builds on the highly successful DB8051C CPU Core, utilizing Digital Blocks Instruction Overlap Architecture, which results in a small VLSI footprint and low Clocks Per Instruction high performance.
8-bit Microcontroller Binary Compliant with MCS 51 Instruction Set
Standard 8051 Architecture: Arithmetic / Logical Unit, Hardware Multiply / Divide, Boolean Processor for Bit Manipulation, 5 Addressing Modes
Enhanced 8051 Architecture: minimum 3 Cycles Per Instruction Execution
Up to 256 bytes of internal Data Memory
Program Memory: User Defined, up to 64 KB (more with Memory Banking); NVM or Configurable SRAM
Data Memory: User Defined, up to 64 KB
User Selected Standard Peripherals: interrupt controller, UART Serial Port, two 16-bit timers, and four 8-bit I/O ports