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2...100 MHz Power amplifier

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IP Name
1065IP1_PA_01G3
Provider

NTLab
Description

2...100 MHz Power amplifier
Categories
Portability
ASIC
Process Node
65nm/TSMC/CMOS
Type
Hard IP
Maturity
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Overview
The PA is based on two class A stages with output attenuator. First stage of amplifier with low nonlinear distortion is used for impedance matching and preamplification of input signal. Second stage is used for final signal amplification and minimizes nonlinear distortion in the operating frequency band. Built-in attenuator is adjusts output power with step 1 dBm in band -55…5 dBm.
External network required to match PA output impedance to 50Om, 75Om, 100Om and for transmittion output signal to antenna with minimal return loss. T The next function of external network is second and third harmonic rejection and PA output signal.
The PA is designed using TSMC 65nm CRN65LP technology.
Features
  • TSMC CMOS 65 nm.
  • A class power amplifier.
  • Wide range variable gain (-55…+5 dBm).
  • Adjustable output power for 50Om, 75Om, 100Om load.
  • Block of adjustable output transistors for fine-tuning.
  • Low nonlinear distortion.
Deliverables
  • Schematic, Layout
  • Extracted view
  • GDS
  • Test bench with saved configurations
  • Documentation
Market Category
Automotive, Communications, Consumer Electronics, Others
Datasheet
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Size
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QIP Rating  This IP is not yet QIP rated.
 
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