XAP4 is a powerful low power 16-bit processor core with a modern architecture designed for ASIC or FPGA implementation. It is particularly applicable battery powered Medical (including in-body) and Wireless Consumer Products. It has excellent processing efficiency and very high code density making it more powerful than 32 bit alternatives and smaller than 8-bit solutions.
At 12k gates and delivering a fast 0.95 DMIPS/MHz. XAP4 is an ideal replacement for 8-bit processors in projects requiring higher performance or reduced program memory cost. It features excellent software portability and is supported by a fully integrated development environment also available from Cambridge Consultants giving the compatibility assurance of a single vendor.
It is ideal for products that demand high performance, low energy and a small footprint.
Cambridge Consultants has developed the 16- and 32-bit XAP® processor family since 1994. These advanced energy-efficient processors are now in over a billion chips, giving licensees a proven competitive advantage in silicon cost and processing performance.
16-bit, 64 kByte processor with load-store architecture. 16-bit registers: Eight general purpose, Program Counter, two Stack Pointers, Vector Pointer and two Breakpoints
High code density (better than many leading 32-bit processors) minimises program memory size for low cost and low energy consumption. 16-bit integer for small processor core and minimal RAM size for stack, heap and variable data
Secure software execution - operating system and interrupt code are protected from user code. User mode and three privileged execution modes: Trusted, Supervisor and Interrupt
Full support for pre-emptive real-time operating systems with guaranteed performance and responsiveness. 16 interrupts including NMI and 32 software exception vectors. Deterministic interrupt response, fully recursive, nested to any depth
Fast 95 DMIPS at 100 MHz. Fast interrupt response time of 11 to 19 clock cycles. Small 12k gates in 0.029 mm2. Dynamic power of 5 µW/MHz (Performance quoted on 65 nm CMOS logic)
Rich set of over 170 instructions in 16 or 32-bit length. Atomic instructions for semaphores, i/o bit set/clear etc. Multi-cycle instructions for function entry and exit, block copy and store, multiply, divide etc. Custom Logic Unit extension
Von Neumann architecture with little-endian organisation. Unified program and data memory in a single address map simplifies Flash memory system design and reduces energy consumption
In-place execution of programs stored in Flash memory. Vector Pointer allows programs to reside anywhere in memory and multiple instances of programs can co-exist. Simplified methodology for program linking and distribution
High code density and efficient instruction set reduces bus traffic. Byte addressing and unaligned data access for efficient memory use. Architecture features simplify porting C programs
The XAP processor family offers a consistent programming model, instruction set and tool chain
Soft core, Verilog RTL delivery. Netlist synthesis for ASIC and also FPGA for development and verification. Example MMU, IVC and CLU code. Test bench and synthesis scripts
Comprehensive xIDE Integrated Development Environment for software development. Includes debugger and Instruction Set Simulator. GNU C compiler, BinUtils assembler
xSIF serial debug interface (can be made JTAG compatible). USB SIF debug pod. SIF explorer application. xEMU FPGA emulator board with XAP4 image
Programmers' manual, instruction set quick reference. Hardware manual, other documentation
RTOS ports available include Micrium uC/OS2 and CMX
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others