The CLP-25 engine bridges the gap between raw cryptographic offload and complete IPsec offload. The IPsec Offload Engine combines hash and cryptographic engines, a special purpose DMA engine, and ESP/AH packet processing logic to offload most of the IPsec protocol from the host processor. The SDMA block alleviates bandwidth on the system bus through dual targeting of the hash and encryption cores. The CLP-25 engine can be tailored to achieve throughput from 40 Mbps up to 1Gbps. The design integrates silicon proven ciphers and hashing cores into a single, configurable IPsec engine. The core requires several memory instances which is not included in the gate count for packet and context memory. Please contact Elliptic for more information on this memory requirement.
AES-CBC mode cipher supporting 128, 192 and 256-bit key sizes.
DES-CBC mode cipher supporting 56 and 168-bit (3DES) key sizes.
HMAC-MD5 and HMAC-SHA-1 mode hash.
Optional AES-GCM mode
AH & ESP mode processing.
Transport mode processing.
Tunnel mode processing.
Extended Sequence Numbers.
Scatter-gather DMA based packet memory architecture.