ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog
Visit IP Talks at DAC 2013 to learn the latest about semiconductor IP

Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com

mDDR Pad Set (90G)

Estimate your chip with this semiconductor IP
Aragio Solutions
Semiconductor IP Vendor InformationView all semiconductor IP from Aragio SolutionsContact Semiconductor IP VendorSemiconductor IP Customer Testimonials Add Semiconductor IP to an IP List

Share
Email Semiconductor IP Datasheet Print Semiconductor IP Datasheet   
IP Name
mDDR
Provider

Aragio Solutions

Description

mDDR Pad Set (90G)

Categories
Portability
ASIC
Process Node
90nm/GLOBALFOUNDRIES/G
Type
Hard IP
Maturity
Please login or register to view this data
Overview
The mDDR IO cell is a bi-directional LVCMOS compatible IO which is designed to interface to a 1.8-volt Mobile DDR SDRAM and be compatible with the 1.8-volt Mobile DDR SDRAM memory specifications. The mDDR IO cell uses internal series termination to provide excellent signal integrity, while avoiding the external parallel termination that significantly increases system power. The mDDR IO cell provides four allowable drive settings for the output drivers to allow the user to select drive strength based on the expected loading on the memory bus. The drive settings are intended to provide full, half, quarter, and one eighth drive strengths while the driver employs slew-rate control to minimize over-shoot and under-shoot of the far-end output waveforms. Utilizing the on-die series termination, the mDDR IO cell provides 30 ~, 45 ~ , 60 ~ and 80 ~ terminating impedances enabling optimum balance to the 50 ~ to 70 ~ board trace T-line impedances, while providing operation up to 167 MHz. Higher frequencies are possible with reduced load capacitance (10 pF to 15 pF max).
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
Please login or register to view this data
Bus Interface
Mobile DDR
Size
Please login or register to view this data
QIP Rating  This IP is not yet QIP rated.
 
     Related IP from Aragio Solutions you may be interested in...
IP Name Description
LVDS LVDS Pad Set (Designed for Common Platform 65LP)
LVDS LVDS Pad Set (Designed for Common Platform 65LPE)
Oscillator Oscillator (90G)
mDDR mDDR Pad Set (90LP)
SubLVDS SubLVDS Pad Set (Designed for Common Platform 65LP)
 
 
Search For Semiconductor Design and Verification IP
Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
SilTerra
SMIC
TSMC
Tower
UMC
X-FAB
advertisement
Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

     Language: Search for Semiconductor Design and Verification IP at ChipEstimate.com English | Search for Semiconductor Design and Verification IP at ChipEstimate.jp Japanese | Search for Semiconductor Design and Verification IP at ChipEstimate.cn Chinese
 
      ChipEstimate.com Chip Planning & IP Portal -- Copyright © 2013 ChipEstimate.com. All rights reserved.
ChipEstimate.com Twitter feed  ChipEstimate.com Semiconductor IP on LinkedIn  ChipEstimate.com Semiconductor IP Channel on YouTube  ChipEstimate.com Semiconductor IP on Facebook  ChipEstimate.com Semiconductor IP on Google+ 


       Feedback  Privacy Policy  Terms of Use  Newsletter & Tech Talk Archive  IP Catalog Site Map