The mDDR IO cell is a bi-directional LVCMOS compatible IO which is designed to interface to a 1.8-volt Mobile DDR SDRAM and be compatible with the 1.8-volt Mobile DDR SDRAM memory specifications. The mDDR IO cell uses internal series termination to provide excellent signal integrity, while avoiding the external parallel termination that significantly increases system power. The mDDR IO cell provides four allowable drive settings for the output drivers to allow the user to select drive strength based on the expected loading on the memory bus. The drive settings are intended to provide full, half, quarter, and one eighth drive strengths while the driver employs slew-rate control to minimize over-shoot and under-shoot of the far-end output waveforms. Utilizing the on-die series termination, the mDDR IO cell provides 30 ~, 45 ~ , 60 ~ and 80 ~ terminating impedances enabling optimum balance to the 50 ~ to 70 ~ board trace T-line impedances, while providing operation up to 167 MHz. Higher frequencies are possible with reduced load capacitance (10 pF to 15 pF max).
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