Find the latest trends and technical details on semiconductor IP from the industry's leading IP vendors
Overview Consumers today demand higher performance, feature-rich applications, and higher quality multimedia content in their mobile devices. These mobile multimedia devices include several processors and co-processors, memories, and sensors, all of which require high-speed data transfers. Having processors and peripheral devices that are able to meet consumers' and designers' requirements is just part of the challenge. To design a high-performance system, designers need to contend with pin count and channel limitations (including the physical dimensions, cost, and package reliability) as well as bandwidth bottlenecks. At the same time, battery operated mobile devices strive for very low power consumption in active and idle periods with quick entry and exit times. The high-speed MIPI® M-PHY is tailored for mobile systems and is becoming a popular physical layer solution. With up to 5,824 Mbps bandwidth, the speed meets devices’ high bandwidth and scalability requirements. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications and employs burst operation to toggle between data transmission and power saving states, effectively reducing power consumption. This white paper discusses how a MIPI M-PHY using High-Speed Gear3 operation can provide power-efficient high-speed links for a variety of mobile chip-to-chip communication standards and protocols, such as JEDEC Universal Flash Storage (UFS), USB 3.0 SuperSpeed Inter-chip (SSIC), and PCI-SIG M-PCIe®, as well as explaining how to solve signal integrity challenges for implementation due to the use of higher speed links.
Introduction A sensor is a device that detects a change in a stimulus and converts it into an electronic signal that can be measured or recorded. The stimulus can be many things, including a physical property, environmental parameter, chemical composition or a location, to name just a few. All sensing elements have nonlinearities that include an intrinsic nonlinearity over sensing range along with offset and sensitivity nonlinearity variations over temperature. Variations in component and circuit characteristics along with chip processing and packaging operations result in deviations of analog circuits and sensors from their target specifications. To optimize the performance of the systems in which these components are placed, it is necessary to "trim" interface circuitry to match a specific analog circuit or sensor. A trimming operation compensates for variations in the analog circuits and sensors due to manufacturing variances of these components. The trimming requirement becomes more important as process nodes shrink due to the increased variability of analog circuit performance parameters at smaller processes, and to both random and systematic variations in key manufacturing steps. This manifests itself as increasing yield loss when chips with analog circuitry migrate to smaller process nodes, since a larger percentage of analog blocks on a chip will not meet design specifications because of the variability in process parameters and layout.
Going wireless It's a trend happening everywhere today, devices are going wireless and connecting to the internet - from the ubiquitous smartphones, tablets and smart TVs to a growing list of consumer electronics products including refrigerators, ovens, games consoles, central heating systems, weather stations, radios and home stereo systems. Indeed the simple home stereo is struggling in the digital world. Little black boxes bristling with audio outputs are proliferating throughout the home, remote controls litter the living room table, docking stations clutter the bedrooms, kitchen and study. Countless inputs and control methods, incompatible interfaces, and way too many wires have created a home entertainment headache
Introduction With an install base of over 3 billion devices worldwide, HDMI has become the de facto multimedia interface for all digital home and mobile multimedia devices. The rapid market growth of HDMI technology has extended beyond digital home and into an increasingly broad array of applications and industries, including mobile applications such as cell phones and tablets, infotainment in automobiles, commercial applications such as digital signage and surveillance, and office applications like projectors, as shown in Figure 1. Per Gartner 2012, the HDMI market grew more than 3x than the overall wired interface market.
It is already a cliché to say that power is the new timing, but that doesn’t mean that it isn’t true. Two huge markets for chips are mobile and data centers. Although mobile is battery-powered and data centers are tethered, both have enormous pressures to keep power down.
The Internet of Things (IoT), sometimes called the Internet of Everything (IoE), refers to an evolving and rapidly expanding global ecosystem comprising the connection via the Internet of all kinds of common objects with embedded electronics, and the processing of the data collected, shared and stored in “The Cloud”. Small embedded controllers, actuators and sensors as well as larger, more complex communications and computing systems will be tasked with acquiring, storing and processing mountains of information. Consequently, this will also significantly increase Internet traffic, along with the need for computing resources to exchange, store and process all the data.
As electronic systems gain in complexity, the complexity of the system’s power management –hardware and software to efficiently and accurately deliver electrical power to the various system components – also rises. Digital Power-Management Integrated Circuits (PMICs) are becoming commonplace in today’s systems to convert unregulated voltages derived from batteries, power lines or other sources, to protected voltage regulators for a variety of loads, including general POL, VCORE and memories.
Designing an integrated circuit - especially one implemented on a modern, aggressive process node - is not for the faint of heart. There are innumerable opportunities for things to go wrong if you're not careful. When you delegate those challenges to a contract design house like Uniquify, you may be relieving yourself of much of the detail, but in doing so, you are placing immense trust in a separate organization.
Modern systems-on-chips (SoCs) are typically implemented in the most advanced process nodes available to take advantage of the smaller and faster properties of that process. This trend has allowed SoC architects to effectively address end users' expectations that each new product generation will offer higher functionality and performance, lower power and, hopefully, lower cost.
This whitepaper describes practical considerations and best practices for Mobile Imaging and Display for Smartphone and Tablet Computing applications and exploresSilicon IP selection and successful adoption based on Arasan extensive customer engagements over the past three years.
To deliver the demanding performance and faster operation of today’s systems—from communication interfaces to high-image-quality video and multimedia systems—consumer applications employ digital signal processing extensively. Data converters form the interface between the real-world analog signals and the digital domain. They are, therefore, an essential element of the complete signal processing chain which is a part of every consumer device.
NAND Flash is the nonvolatile memory used in virtually all mobile devices. (smartphones, tablets, cameras, game controllers). High performance products (Tablets and smartphones) place increasing demands on NAND Flash device capacity, cost and bandwidth. To meet these demands, component and application processor designers must utilize a complex combination of electronic hardware and software. As a result benchmarking NAND Flash at the component and system level is a key element in successful product design.
As consumer electronic devices push for higher performance and more functionality at lower cost and lower power, system-on-chip (SoC) designers need to be as efficient as possible in choosing the right technology for a specific application. Specifically with the emergence of near field communication (NFC) technology and the continued proliferation of HDMI into every digital video interface, there is a growing need for embedded multiple time programmable (MTP) non-volatile memory (NVM) to execute these functions.
With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar FETs (also called “planar CMOS”) as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic power, intra-die variability, and retention voltage for SRAMs.
Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction. These techniques boost the performance of the processor by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit such that each additional instruction is explicitly part of the instruction mnemonic, or it can be implicit, where the number and type of operations are encoded into the instruction. While explicit parallelism is suitable in certain contexts, implicit parallelism offers inherent advantages that enhance performance and simplify coding, making it a better option in many cases.
In recent years, embedded non-volatile memory (NVM) has expanded beyond code storage for embedded applications and microcontrollers into data applications ranging from high-volume consumer products to high-reliability automotive and industrial products. As the application space for embedded NVM expands, the requirements also expand beyond what is most efficiently addressed by embedded flash technology.These new applications and requirements are bringing new technologies (and technology suppliers) together with new users in the embedded NVM marketplace.
The reduction in fabrication costs now makes custom analog SoCs a real option for more product managers. All the advantages afforded by SoCs - including secure innovative designs with differentiating features - are now available to a wider range of products. In this paper these advantages are placed alongside the potential savings in BOM and illustrate a strong business case for investment in SoC. Three recent custom analog SoC designs, where meeting serious technical challenges resulted in significant cost per unit reductions, are described. These reductions against projected sales made the SoC solution the smartest business decision. Going the SoC route is not without its risks, so partnering with a proven SoC design house that brings knowledge of available IP and experience of subsystem development makes sense.
What do all of these things have in common? They were key topics addressed by Cadence...