Agilent, NVIDIA accelerate signal integrity simulations EDN To accelerate signal integrity simulations faster than previously possible, Agilent Technologies Inc said Tuesday afternoon that it is working with Nvidia to develop a commercial software release of a GPU-enabled Advanced Design System Transient Convolution Simulator, based on Nvidia's Compute Unified Device Architecture-based GPU.
IP selection and power supplies EDN The failure to fully embrace just one of the two competing power-analysis standards has caused confusion and uncertainty among IP users about power-strategy compatibility.
Algotronix appoints Nisko-IES for Israel Friday, 22 August 2008
Algotronix Ltd., Edinburgh, UK has appointed Nisko-IES as its distributor in Israel.
The agreement provides for Nisko-IES to handle the Algotronix line of Advanced Encryption Standard (AES) products. These are low cost, high performance IP cores that fit into all popular FPGAs or ASICs.
“We are very pleased to announce this agreement with Nisko-IES,” said Tom Kean, Managing...
Accellera approves analog, mixed-signal standard EDN To allow the development of standard and tightly integrated Verilog-AMS modules and allow EDA software tool developers to implement EDA tools without ambiguities in the language interpretation, EDA standards organization Accellera announced today that it has approved a new version of its Verilog-analog mixed-signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analog and mixed-s...
Altera, Mentor team up to support avionics, military apps EDN In support of the growing number of avionics and military applications requiring DO-254-certifiable components, San Jose-based programmable logic device company Altera Corp and Wilsonville, Ore-based IC design tool supplier Mentor Graphics Corp reported today that they are doing joint work to develop tools and methodologies for use in creating DO-254-certifiable IP that targets Altera's FPGA an...
Virtualization and multicore x86 CPUs EDN The aggressive multicore roadmaps of the x86 chip vendors point to virtualization becoming ubiquitous in the near future. I/O support is the last remaining performance bottleneck for heavily virtualized data-center systems. Fortunately, a number of proven techniques under active development and standardization hope to keep stride with the increasing number of available CPU cores.
Structured-ASIC option reaches 45-nm node EDN Structured-ASIC pioneer eASIC announced today a family of fast-turn ASIC products at 45 nm, combining the zero-NRE (non-recurring expenses) and six-week turnaround of their via-programmed architecture with the performance, density, and power characteristics of the industry's most advanced production node.
Intel details PC graphics-aimed 'Larrabee' EDN Santa Clara, Calif-based chip giant Intel Corp will present a paper at the Siggraph 2008 conference being held next week in Los Angeles that details features and capabilities for its forthcoming multi-core “Larrabee” architecture which includes a new approach to the software rendering 3-D pipeline, a many-core programming model and performance analysis for several applications.
Intel marches once again into microcontroller market EDN Combining a single processor-core complex, North- and South-bridge functions, application-specific peripheral blocks, and in some cases an application accelerator, the chips in the family will create an x86-instruction-set alternative to the rainbow of ARM- and MIPS-based SOCs, at least for systems that can tolerate the considerable power and memory footprint involved.
Where is EDA going now? EDN Some important changes have been altering the EDA landscape for years, and these changes'in the geographic composition of the chip-design community and in the nature of the chip-design process'are now impossible to conceal.
Your chip in half the time? EDN GUEST OPINION: A project's commercial success depends on designers' ability to deliver silicon on time. That's why the industry recognizes the growing importance of time to results.
Nanoimprint lithography stamps out encouraging results EDN Researchers at NIST (National Institute of Standards and Technology) have put NIL (nanoimprint lithography)'a potential next-generation IC-fabrication technology'through its paces and pronounced the technique capable of accurately producing delicate insulating structures on advanced ICs. NIST reports that NIL, which essentially embosses a pattern onto a thin film atop a semiconducto...
Spansion, Virident aim to slash power in server farms EDN By creating a new category of flash with one-eighth the average operating power and eight-times the bit density of DRAM DIMMs, Spansion hopes to enable a sea change in the way server farm managers implement memory. And by making this new flash device transparent to the rest of the server hardware and software, Virident intends to make the switch-over from DRAM to flash painless and profitable f...
Atrenta announces 1Team-Genesis,
collaborates with STMicroelectronics EDN Atrenta Inc announced at the 45th DAC (Design Automation Conference) the availability of 1Team-Genesis, which focuses on the capture of design specifications, the automated generation of design descriptions and documentation, the rapid exploration of design alternatives, and “correct-by-construction” chip assembly.
The megapixel race: a chip designer's point of view EDN As CMOS image sensors have migrated from low-end applications to multimegapixel cameras, emphasis has shifted from integrating digital circuits to the fundamental design of the pixel itself.
