InCyte™ Chip Estimator

The InCyte™ Chip Estimator provides IC design teams, architects and management with the ability to visualize tradeoffs throughout the chip design cycle. Bringing IP and manufacturing data to bear on the earliest stage of chip planning, the InCyte Chip Estimator enables earlier and more informed decision-making in the context of critical decisions affecting chip performance, functionality and cost. The system helps users explore a wide range of chip architecture options in literally seconds including selection of IP, technology nodes and manufacturing technologies, low power strategies, packaging and much more. Using the InCyte Chip Estimator to develop and optimize chip specifications gives accurate insight into chip size, power, leakage, performance and cost, as estimation results typically correlate well with final silicon.

InCyte Chip Estimator users enter a high-level design specification, including selection of gate counts, performance goals, off-chip bus connections, memory configurations and optional connectivity. They then select IP to be considered either by importing IP Lists they build by searching and selecting IP at ChipEstimate.com, choosing from the InCyte Chip Estimator's extensive integrated catalog or entering in custom IP definitions. After the initial specification is defined, the InCyte Chip Estimator returns a complete datasheet with estimations of final silicon including die area, performance, power, leakage, yield, package recommendations and production chip cost.

Whether you're starting with a complete chip specification or just a high level block diagram, the InCyte Chip Estimator can provide you with meaningful and valuable feedback in seconds.

See how ARM IP can be used in a chip estimation using InCyte.

Chip Planning Solutions

Various chip planning products are available ranging from a free entry-level version to comprehensive systems with more accurate data modeling and greater analysis and output capabilities.

InCyte Chip Estimator Starter Edition is the free downloadable, entry-level system used for project feasibility analysis at the early architectural stage of chip planning. The tools bases estimates on industry average IP library and process models, providing early predictions of chip die size, power, and leakage. Results are generally accurate enough for very rough analysis but should not be used for production IC designs or as the basis for technical or economic decisions. Learn more...

Cadence InCyte Chip Estimator is a production quality, silicon provide accurate chip estimation and planning system from Cadence Design Systems. It is used to develop and refine chip specifications, manage die and packaged chip costs, and aid in the exploration of various IP and manufacturing options. InCyte Chip Estimator estimates are based on technology models created from design kits provided by leading IP suppliers and semiconductor manufacturers for increased accuracy. The tool guides users in the what-if analysis process, optimizing their specifications to achieve functionality and performance goals. In addition to die size, power, and leakage estimates, InCyte Chip Estimator allows users to input and assess performance targets and leverage available connectivity data for the most realistic chip estimation possible.

The system also includes the ability to use block diagrams as part of the specification input, and assists users in finding the IP that meets their functional and performance requirements. Rapid what-if analysis enables quick iterations to compare and refine design plans to achieve the optimal balance of functionality, performance and cost. Comprehensive technical reports and chip budgetary quotes are generated and direct integration into leading EDA implementation tools enables convergence from initial design estimations to final silicon. Learn more...

Cadence Chip Planning System offers a complete and customizable chip planning and IP re-use solution for semiconductor and electronic systems companies. The solution is used to generate refined chip specifications, accurate IC quotations and to customize chip estimations to meet their corporation's internal requirements. The Chip Planning System allows for estimation with custom IP and manufacturing processes and for tuning of technology models for the highest possible accuracy. The system resides within a customer's secure corporate network, providing users with a local, dedicated chip estimation environment. The Chip Planning System can be linked into internal IP and technology databases and tightly integrated into a company's chip implementation flow. Learn more...

Resources

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Blogs

  • CDN LIVE Conference
  • Moore's Cycle, Fifth Horseman, Mixed Signals, and IP Stress
  • IP Insider Blog-By John Blyler
    Posted 3.23.2013
  • What do all of these things have in common? They were key topics addressed by Cadence...